Lewis C Eggebrecht

US Patent:

44370920, Mar 13, 1984

Filed:

Aug 12, 1981

Appl. No.:

6/292069

Inventors:

Mark E. Dean - Boynton Beach FL
Lewis C. Eggebrecht - Rochester MN
David A. Kummer - Boca Raton FL
Jesus A. Saenz - Coral Springs FL

Assignee:

International Business Machines Corporation

International Classification:

G09G 128

US Classification:

340703

Abstract:

A central processing unit (10) loads a border register (36) with four color bits representing digital color signals to be used in determining the color of only the border area (40) surrounding the video area (42) of a cathode ray tube display screen (44). A BORDER CONTROL TIME signal is generated at the appropriate times in the horizontal and vertical scanning periods of the cathode ray tube to apply the digital color border signals (R, G, G, I) to a composite video signal generator (38) which generates the composite video signal for a TV set (14) or a TV monitor.

US Patent:

44438478, Apr 17, 1984

Filed:

Feb 5, 1981

Appl. No.:

6/231653

Inventors:

David J. Bradley - Boca Raton FL
Lewis C. Eggebrecht - Boca Raton FL
Dennis S. Gibbs - Lighthouse Point FL
Donald J. Kostuch - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

364200

Abstract:

In a computer system, paging operates and a method of use thereof are provided for extending the addressing capability of a processor by using a page register. The page register includes means for storing different codes for different operations to be performed on the memory. The memory is divided into four groups of memory within 2. sup. n addresses such that there is paged and unpaged ROM and pages and unpaged RAM. The unpaged ROM and RAM include only a single block which is directly addressed by the n bit address bus. The paged ROM and RAM includes a plurality of blocks or pages, one of which is selected to be addressed by the page register. The page register responds to the address bus and to signals from the processor defining the memory operation to be performed by providing page signals, selecting one page of paged memory. The method of using the paging apparatus includes creating a table in the unpaged RAM of all routines in the paged memory blocks and using the table to transfer from one routine to another. Within the table is a code identifying the page in which the new routine exists and an offset into that page used to determine the address in that page of the new routine.

US Patent:

45569525, Dec 3, 1985

Filed:

Aug 12, 1981

Appl. No.:

6/292075

Inventors:

James A. Brewer - Delray Beach FL
Lewis C. Eggebrecht - Rochester MN
David A. Kummer - Boca Raton FL
Patricia P. McHugh - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

364900

Abstract:

In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.