Lewis A Phillips

US Patent:

39939359, Nov 23, 1976

Filed:

Dec 16, 1974

Appl. No.:

5/533396

Inventors:

Lewis A. Phillips - Rockville MD
George J. Leiby - Mount Airy MD

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H05K 104

US Classification:

317101C

Abstract:

A printed circuit board or the like for electrical apparatus has edge connectors for insertion into a terminal or group of terminals for communication of electrical signals from the terminals to the board and vice versa. Some contacts on the board edge are recessed slightly from the edge so that certain electrical connections may be made prior to others.

US Patent:

51245698, Jun 23, 1992

Filed:

Oct 18, 1990

Appl. No.:

7/599460

Inventors:

Lewis A. Phillips - Rockville MD

Assignee:

Star Technologies, Inc. - Sterling VA

International Classification:

H03K 500
H03K 513

US Classification:

307262

Abstract:

A phase-lock loop scheme which can be implemented in an application specific integrated circuit using CMOS elements is disclosed which is directed to controlling a plurality of slave gate array circuits such that each of the master gate array circuit and the slave gate array circuits are clocked at the same time and are within a fixed time delay from a device reference clock signal. The master gate array circuit receives the input clock synchronization signal from the master clock of the device containing the master and gate array circuits and produces an internal clock signal which is then sent to each of the slave gate array circuits, by means of equal delay paths. The phase-lock loop circuitry utilized by each of the gate arrays can be implemented on program logic array chips along with the logic which receives the synchronized clock signals generated by the respective phase-lock loops of each of the gate array chips. Both fixed and automatic gain and damping controls for the phase-lock loops are also disclosed.