Li Li

US Patent:

6445597, Sep 3, 2002

Filed:

Jun 28, 2001

Appl. No.:

09/894328

Inventors:

Jeffrey J. Boylan - Richardson TX
Mark E. Jacobs - Dallas TX
Li Li - Richardson TX

Assignee:

Tyco Electronics Logistics AG - Steinbach

International Classification:

H02M 3335

US Classification:

363 2106, 363 70, 363 89

Abstract:

A local loop control system and method of operating the same for use with a power converter. The power converter includes a first output coupled to a first synchronous rectifier circuit and a second output coupled to a second synchronous rectifier circuit. The power converter employs a main controller configured to regulate a voltage proportional to a weighted sum of the first and go second outputs. In one embodiment, the local loop control system includes: (1) a first output controller configured to regulate a voltage at the first output and (2) a second output controller configured to regulate a voltage at the second output, one of the first and second output controllers configured to reduce a drive signal to a corresponding one of the first and second synchronous rectifier circuits when a corresponding voltage at one of the first and second outputs exceeds a voltage proportional to the weighted sum.

US Patent:

6461967, Oct 8, 2002

Filed:

Jul 16, 2001

Appl. No.:

09/907296

Inventors:

Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438705, 216 38, 216 87, 438692, 438753

Abstract:

Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

US Patent:

6519166, Feb 11, 2003

Filed:

Oct 27, 2001

Appl. No.:

10/046007

Inventors:

Li Li - Richardson TX 75081

International Classification:

H02M 3335

US Classification:

363 2117

Abstract:

An apparatus for effecting a preload operation of an electrical converter device that includes a primary circuit section inductively coupled with at least one secondary circuit section presenting at least one output voltage at at least one output locus includes: (a) a load coupled with at least one selected output locus of the at least one output locus; (b) a switch device electrically coupling the load within the at least one secondary circuit section; and (c) a timer device coupled with the switch device. The timer device orients the switch device to electrically disconnect the load from the at least one secondary circuit section after a predetermined time interval elapses.

US Patent:

6596642, Jul 22, 2003

Filed:

Jul 11, 2002

Appl. No.:

10/193801

Inventors:

Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438705, 216 38, 216 87, 438692, 438753

Abstract:

Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

US Patent:

6596648, Jul 22, 2003

Filed:

Jul 11, 2002

Appl. No.:

10/193850

Inventors:

Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438745, 438692, 438756

Abstract:

Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

US Patent:

6599840, Jul 29, 2003

Filed:

Jul 11, 2002

Appl. No.:

10/194833

Inventors:

Zhiqiang Wu - Plano TX
Li Li - Meridian ID
Thomas A. Figura - Nishiwaki, JP
Kunal R. Parekh - Boise ID
Pai-Hung Pan - Boise ID
Alan R. Reinberg - Westport CT
Kin F. Ma - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438705, 438752, 438753

Abstract:

Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

US Patent:

6693812, Feb 17, 2004

Filed:

Aug 12, 2002

Appl. No.:

10/217011

Inventors:

Li Li - Dallas TX
John F. Steel - Plano TX
Thomas G. Wang - Plano TX

Assignee:

Tyco Electronics Power Systems Inc. - Mesquite TX

International Classification:

H02M 3335

US Classification:

363 97

Abstract:

The present invention provides a bias supply selection circuit employable with a linear regulating device configured to provide a first bias supply voltage and a main bias supply stage configured to provide a second bias supply voltage. In one embodiment, the bias supply selection circuit includes a voltage monitoring circuit configured to monitor a level of the second bias supply voltage and to provide a control voltage proportional to the level. Additionally, the bias supply selection circuit includes a controllable switching circuit, coupled to the voltage monitoring circuit, configured to select the second bias supply voltage by deactivating the linear regulating device when the control voltage reaches a predetermined value.

US Patent:

7085716, Aug 1, 2006

Filed:

Oct 26, 2000

Appl. No.:

09/696685

Inventors:

Stijn Van Even - Jamaica Plain MA, US
Li Li - Bedminster NJ, US
Xianju Du - Acton MA, US
Puming Zhan - Acton MA, US

Assignee:

Nuance Communications, Inc. - Burlington MA

International Classification:

G10I 15/26

US Classification:

704235, 704251

Abstract:

A method is described that corrects incorrect text associated with recognition errors in computer-implemented speech recognition. The method includes the step of performing speech recognition on an utterance to produce a recognition result for the utterance. The command includes a word and a phrase. The method includes determining if a word closely corresponds to a portion of the phrase. A speech recognition result is produced if the word closely corresponds to a portion of the phrase.