Lieu Thi Nguyen

US Patent:

58256598, Oct 20, 1998

Filed:

Jun 16, 1995

Appl. No.:

8/491433

Inventors:

Lieu T. Nguyen - San Jose CA
Kwok Ming Yue - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2350

US Classification:

364490

Abstract:

The present invention provides a local rip-up and reroute (LRR) method to reduce the number of open nets after the initial routers have been applied. Two main tasks are performed under this method. The first task is to identify a locally blocked pin and rip up wire segments in an area around the cell having the locally blocked pin. The second task is to reroute the now freed locally blocked pin. In the first task, an open net is read from the list of open nets. The pins of this open net are identified and determined if they are locally blocked. A pin is considered as locally blocked if a routing path, starting from the pin, cannot be found within N grid point expansions. If a pin is locally blocked, segments of wires within or at the boundary of a predefined bounding box are removed (or ripped-up)--except for two situations. The first exception is that a wire that is connected to a pin is not ripped-up. The second exception is that a SM wire segment that occupies only one horizontal track running through both boundaries of the bounding box is not ripped-up.

US Patent:

60284404, Feb 22, 2000

Filed:

Mar 20, 1998

Appl. No.:

9/045190

Inventors:

Wolfgang Roethig - San Jose CA
Lieu T. Nguyen - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3126

US Classification:

324765

Abstract:

The present invention provides an analytical solution for voltage drop and current density calculation based on design-specific current consumption. The new technique calculates voltage drop and current density at all desired points of the power supply mesh. One application of the method is power mesh sizing by scaling the mesh resistance by the ratio between allowed voltage drop budget and the maximum of the calculated voltage drop. The designer can easily obtain the maximum allowed resistance of a uniform mesh which meets exactly the voltage drop budget, taking into account the design-specific spatial distribution of current consumption. Since the computational cost of the new methodology is negligible, e. g. as compared to prior art methods of analysis, this invention is suitable for implementation embedded in an RTL floorplan tool for fast, interactive tradeoff between floorplan location and voltage drop.