Lin Chen

US Patent:

7855863, Dec 21, 2010

Filed:

Nov 19, 2008

Appl. No.:

12/274085

Inventors:

Dening Wang - McKinney TX, US
Yuan Gu - Dallas TX, US
Lin Chen - Mountain View CA, US
Jonathan Scott Brodsky - Richardson TX, US
Wei-Chung Wu - Richardson TX, US
Wenliang Chen - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 9/00
H01C 7/12
H02H 1/00
H02H 1/04
H02H 3/22
H02H 9/06

US Classification:

361 56, 361118

Abstract:

Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

US Patent:

7948316, May 24, 2011

Filed:

May 28, 2009

Appl. No.:

12/473978

Inventors:

Wei-Chung Wu - Richardson TX, US
Lin Chen - San Jose CA, US
Yuan Gu - Dallas TX, US
Kae Ann Wong - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/26

US Classification:

330267, 330277

Abstract:

An amplifier is provided that includes an output portion that sources and sinks current associated with an output load and an amplification portion that is biased by a relatively small bias current with respect to an output current of the amplifier. The amplification portion provides an amplified output signal to the output portion. The amplifier further comprises at least one impedance component coupled between the output portion and the amplification portion to alter at least one pole associated with the amplifier to mitigate instability of the amplifier related to the relatively small bias current.

US Patent:

20040040857, Mar 4, 2004

Filed:

May 31, 2003

Appl. No.:

10/448982

Inventors:

Lin Chen - Plano TX, US
Thomas Taylor - Portland OR, US

Assignee:

Semitool, Inc. - Kalispell MT

International Classification:

C25D005/02

US Classification:

205/123000, 205/183000

Abstract:

A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.