Lin Yuan Cheng

US Patent:

8169022, May 1, 2012

Filed:

Jun 18, 2010

Appl. No.:

12/818232

Inventors:

Lin Cheng - Chapel Hill NC, US
Michael Mazzola - Starkville MS, US

Assignee:

SS SC IP, LLC - Jackson MS

International Classification:

H01L 29/66

US Classification:

257335, 257 77, 257287, 257E27148, 257E29265, 257E21421, 438192, 438194, 438186

Abstract:

Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

US Patent:

8338255, Dec 25, 2012

Filed:

Jun 18, 2010

Appl. No.:

12/818281

Inventors:

Lin Cheng - Chapel Hill NC, US

Assignee:

SS SC IP, LLC - Jackson MS

International Classification:

H01L 21/336

US Classification:

438269, 257135, 257E21445

Abstract:

Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described.

US Patent:

20120223330, Sep 6, 2012

Filed:

Mar 3, 2011

Appl. No.:

13/039441

Inventors:

Sarit Dhar - Cary NC, US
Lin Cheng - Chapel Hill NC, US
Anant Agarwal - Chapel Hill NC, US

Assignee:

CREE, INC. - Durham NC

International Classification:

H01L 29/161
H01L 21/22

US Classification:

257 77, 438542, 257E29084, 257E21135

Abstract:

Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.

US Patent:

20120280252, Nov 8, 2012

Filed:

May 6, 2011

Appl. No.:

13/102510

Inventors:

Doyle Craig Capell - Hillsborough NC, US
Lin Cheng - Chapel Hill NC, US
Sarit Dhar - Cary NC, US
Charlotte Jonas - Morrisville NC, US
Anant Agarwal - Chapel Hill NC, US
John Palmour - Cary NC, US

International Classification:

H01L 29/12
H01L 29/06
H01L 29/772

US Classification:

257 77, 257329, 257494, 257E29068, 257E29005, 257E29262

Abstract:

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

US Patent:

20120280270, Nov 8, 2012

Filed:

May 16, 2011

Appl. No.:

13/108440

Inventors:

Doyle Craig Capell - Hillsborough NC, US
Lin Cheng - Chapel Hill NC, US
Sarit Dhar - Cary NC, US
Charlotte Jonas - Morrisville NC, US
Anant Agarwal - Chapel Hill NC, US
John Palmour - Cary NC, US

International Classification:

H01L 29/739
H01L 29/78

US Classification:

257133, 257288, 257E29197, 257E29255

Abstract:

A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

US Patent:

20120326163, Dec 27, 2012

Filed:

Sep 9, 2011

Appl. No.:

13/229276

Inventors:

Sarit Dhar - Raleigh NC, US
Lin Cheng - Chapel Hill NC, US
Anant Agarwal - Chapel Hill NC, US
John Williams Palmour - Cary NC, US
Jason Gurganus - Raleigh NC, US

Assignee:

CREE, INC. - Durham NC

International Classification:

H01L 29/161
H01L 29/49
H01L 21/28

US Classification:

257 77, 438591, 257750, 257E29084, 257E2119, 257E2915

Abstract:

Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

US Patent:

20130026493, Jan 31, 2013

Filed:

Feb 6, 2012

Appl. No.:

13/366658

Inventors:

Lin Cheng - Chapel Hill NC, US
Anant K. Agarwal - Chapel Hill NC, US
Michael John O'Loughlin - Chapel HIll NC, US
John Williams Palmour - Cary NC, US

Assignee:

CREE, INC. - Durham NC

International Classification:

H01L 29/24

US Classification:

257 77, 257E29104

Abstract:

The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mΩcm) and even more preferably less than 5 mΩcm. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 mΩcmand even more preferably less than 7 mΩcm. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 mΩcmand even more preferably less than 10 mΩcm. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.

US Patent:

20130140585, Jun 6, 2013

Filed:

Jan 28, 2013

Appl. No.:

13/751434

Inventors:

Power Integrations, Inc. - San Jose CA, US
Lin Cheng - Durham NC, US

Assignee:

Power Integrations, Inc. - San Jose CA

International Classification:

H01L 29/872

US Classification:

257 77, 257475

Abstract:

A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.