Linda Faye Hurd

US Patent:

20220382555, Dec 1, 2022

Filed:

Jun 14, 2022

Appl. No.:

17/839856

Inventors:

- Santa Clara CA, US
BARATH LAKSHMANAN - Chandler AZ, US
TATIANA SHPEISMAN - Menlo Park CA, US
Joydeep Ray - Folsom CA, US
Ping T. Tang - Edison NJ, US
Michael Strickland - Sunnyvale CA, US
Xiaoming Chen - Shanghai, CN
Anbang Yao - Beijing, CN
Ben J. Ashbaugh - Folsom CA, US
Linda L. Hurd - Cool CA, US
Liwei Ma - Beijing, CN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06F 9/30
G06F 13/42
G06F 13/40
G06N 20/00
G06T 1/20
G06N 3/04
G06N 3/063
G06N 3/08
G06N 20/10
G06F 9/50
G06F 15/80
G06N 3/00

Abstract:

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

US Patent:

20190146800, May 16, 2019

Filed:

Dec 20, 2018

Appl. No.:

16/227645

Inventors:

- Santa Clara CA, US
BARATH LAKSHMANAN - Chandler AZ, US
TATIANA SHPEISMAN - Menlo Park CA, US
Joydeep Ray - Folsom CA, US
Ping T. Tang - Edison NJ, US
Michael Strickland - Sunnyvale CA, US
Xiaoming Chen - Shanghai, CN
Anbang Yao - Beijing, CN
Ben J. Ashbaugh - Folsom CA, US
Linda L. Hurd - Cool CA, US
Liwei Ma - Beijing, CN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06N 20/00
G06F 15/80
G06F 13/42
G06F 9/30
G06F 13/40
G06T 1/20
G06N 3/00
G06F 9/50

Abstract:

One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

US Patent:

20190130743, May 2, 2019

Filed:

Dec 27, 2018

Appl. No.:

16/233922

Inventors:

- Santa Clara CA, US
Johanna Swan - Scottsdale AZ, US
Annie Foong - Aloha OR, US
Karla Saur - Portland OR, US
Hassnaa Moustafa - Portland OR, US
Rita H. Wouhaybi - Portland OR, US
Linda Hurd - Cool CA, US
Rajashree Baskaran - Portland OR, US

International Classification:

G08G 1/0968
H04W 4/44
G01C 21/34
G01C 21/28
G08G 1/0962
G08G 1/0965

Abstract:

Techniques are disclosed herein for providing guidance for autonomous vehicles in areas of low network connectivity, such as rural areas. According to an embodiment, a guidance system receives a request to exchange data with a vehicle within a specified radius thereof over a wireless connection (e.g., a radio frequency protocol-based connection). The data is stored by the guidance system and is indicative of navigation information within the specified radius. The guidance system transmits the stored data to the vehicle. The guidance system also receives, from the vehicle, data indicative of navigation information for a path previously passed by the vehicle.

US Patent:

20180307494, Oct 25, 2018

Filed:

Apr 24, 2017

Appl. No.:

15/494773

Inventors:

- Santa Clara CA, US
BARATH LAKSHMANAN - Chandler AZ, US
TATIANA SHPEISMAN - Menlo Park CA, US
Joydeep Ray - Folsom CA, US
Ping T. Tang - Edison NJ, US
Michael Strickland - Sunnyvale CA, US
Xiaoming Chen - Shanghai, CN
Anbang Yao - Beijing, CN
Ben J. Ashbaugh - Folsom CA, US
Linda L. Hurd - Cool CA, US
Liwei Ma - Beijing, CN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06F 9/30
G06F 13/42
G06F 13/40
G06N 99/00

Abstract:

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.

US Patent:

20180307495, Oct 25, 2018

Filed:

Nov 21, 2017

Appl. No.:

15/819167

Inventors:

- Santa Clara CA, US
BARATH LAKSHMANAN - Chandler AZ, US
TATIANA SHPEISMAN - Menlo Park CA, US
Joydeep Ray - Folsom CA, US
Ping T. Tang - Edison NJ, US
Michael Strickland - Sunnyvale CA, US
Xiaoming Chen - Shanghai, CN
Anbang Yao - Beijing, CN
Ben J. Ashbaugh - Folsom CA, US
Linda L. Hurd - Cool CA, US
Liwei Ma - Beijing, CN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06N 99/00
G06F 13/40
G06F 13/42
G06F 9/30

Abstract:

One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.