Ling Y Yang

US Patent:

20130320560, Dec 5, 2013

Filed:

May 28, 2013

Appl. No.:

13/903323

Inventors:

Ling Yang - San Jose CA, US
Chanh Tran - San Jose CA, US
Ying Ji - San Jose CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H01L 23/48
H01L 21/768

US Classification:

257774, 438637

Abstract:

An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

US Patent:

20140040674, Feb 6, 2014

Filed:

Aug 1, 2012

Appl. No.:

13/564610

Inventors:

Mark Pereira - Livermore CA, US
Ling Yang - Pleasanton CA, US
Govendra Gupta - Gandhi Nagar Jammu, IN

International Classification:

G06F 11/07

US Classification:

714 49, 714E11024

Abstract:

An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

US Patent:

20140040709, Feb 6, 2014

Filed:

Aug 1, 2012

Appl. No.:

13/564586

Inventors:

Mark Pereira - Livermore CA, US
Ling Yang - Pleasanton CA, US
Govendra Gupta - Gandhi Nagar Jammu, IN

International Classification:

H03M 13/09
G06F 11/10

US Classification:

714807, 714E11032

Abstract:

An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

US Patent:

20210211351, Jul 8, 2021

Filed:

Dec 17, 2020

Appl. No.:

17/124799

Inventors:

- Suwanee GA, US
Ling Yang - Pleasanton CA, US
Vignesh Hariharan - Fremont CA, US
Robin S. Wong - Alamo CA, US

Assignee:

ARRIS Enterprises LLC - Suwanee GA

International Classification:

H04L 12/24
H04L 12/423
H04L 12/935

Abstract:

An electronic device includes multiple networking devices arranged in a stack. The networking devices may include configurable ports, where a given configurable port in the configurable ports may be configured as a data port or a stacking port. During operation, a networking device in the stack may be designated as a master in the stack. In response, the networking device may provide one or more probe messages to determine a state of the networking devices, where the state includes one or more connections among the networking devices. Then, the networking device may verify that the one or more connections are correct. When the one or more connections are correct, the networking device may define a subset of the configurable ports in the networking devices as stacking ports.

US Patent:

20170098595, Apr 6, 2017

Filed:

Oct 3, 2016

Appl. No.:

15/284295

Inventors:

- Sunnyvale CA, US
Ling Yang - San Jose CA, US
Chanh Tran - San Jose CA, US
Ying Ji - San Jose CA, US

International Classification:

H01L 23/48
H01L 25/065
H01L 21/768
H01L 23/528

Abstract:

An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.

US Patent:

20150221589, Aug 6, 2015

Filed:

Apr 9, 2015

Appl. No.:

14/683073

Inventors:

- Sunnyvale CA, US
Ling Yang - San Jose CA, US
Chanh Tran - San Jose CA, US
Ying Ji - San Jose CA, US

International Classification:

H01L 23/528
H03K 5/1252
H01L 23/48

Abstract:

An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.