Ling L Yu

US Patent:

8081503, Dec 20, 2011

Filed:

Feb 27, 2009

Appl. No.:

12/395598

Inventors:

Andy Nguyen - San Jose CA, US
Ling Yu - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 11/00

US Classification:

365154, 365 4911, 365156, 365174, 36518916, 36518905, 36518911, 365202, 36523006, 36523003, 36523008, 36523316, 36523317

Abstract:

Arrays of memory elements may have data lines and address lines. Each memory element may have five transistors. An address decoder may receive an undecoded address signal and may produce a corresponding decoded address signal. The decoded version of the address signal may be used in addressing the memory elements in the memory array. The memory array may be loaded with configuration data. Loaded memory elements may each provide a static output control signal that configures a programmable logic transistor in programmable logic. The memory elements may be powered with an elevated voltage during normal operation. Boosted address signals may be used when addressing the memory array. The address decoder may contain circuitry that is responsive to a clear control signal and an address output enable signal. The memory element array may be cleared by asserting the clear control signal and address output enable signal.

US Patent:

8193836, Jun 5, 2012

Filed:

May 9, 2011

Appl. No.:

13/103832

Inventors:

Andy Nguyen - San Jose CA, US
Ling Yu - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 5/22

US Classification:

327 73, 327 72, 327 77, 327 87

Abstract:

A circuit includes a comparator, a resistor divider, a control circuit, a multiplexer, and a programmable gain amplifier. The comparator is operable to measure an internal voltage of the circuit based on a selected reference voltage. The resistor divider is operable to generate reference voltages. The control circuit is operable to generate a select signal based on an output signal of the comparator. The multiplexer is operable to select one of the reference voltages from the resistor divider as the selected reference voltage based on the select signal. The programmable gain amplifier is configurable to generate a compensation voltage to compensate for an offset voltage of the comparator. The compensation voltage is provided to an input of the comparator.

US Patent:

8232826, Jul 31, 2012

Filed:

Jan 25, 2010

Appl. No.:

12/692847

Inventors:

Andy Nguyen - San Jose CA, US
Ling Yu - Cupertino CA, US
Ryan Fung - Mississauga, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 11/26

US Classification:

327261, 327276

Abstract:

A circuit with N primary outputs and a delay chain with M selection multiplexers. M can be less than N, and M is based on the number of primary outputs that simultaneously require a delayed signal from the delay chain. The N primary outputs may include core outputs and/or registers. Each of the M selection multiplexers feed directly or indirectly a subset of the N primary outputs.

US Patent:

8497712, Jul 30, 2013

Filed:

May 18, 2012

Appl. No.:

13/475937

Inventors:

Andy Nguyen - San Jose CA, US
Ling Yu - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 5/22

US Classification:

327 73, 327 72, 327 77, 327 87

Abstract:

A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator.

US Patent:

20090261862, Oct 22, 2009

Filed:

Apr 17, 2008

Appl. No.:

12/105262

Inventors:

Andy Nguyen - San Jose CA, US
Ling Yu - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 5/22

US Classification:

327 73

Abstract:

A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

US Patent:

20210338074, Nov 4, 2021

Filed:

Oct 25, 2018

Appl. No.:

17/285449

Inventors:

- Hong Kong, CN
Ling Yu - Fremont CA, US

International Classification:

A61B 3/032
A61B 3/103
A61B 3/028
A61B 3/00

Abstract:

Methods and systems am disclosed in which an optical diagnosis of an eye's optical image quality is performed using a simulated retinal image. An objective measurement of a total wave aberration is obtained, and residual aberrations are computed by subtracting a sphero-cylindrical correction from the total wave aberration. The simulated retinal image is computed by computing a point-spread function from the residual aberrations and convolving the computed point-spread function with an acuity chart. The optical diagnosis includes at least one of: determining excess aberrations, ranking optics of the eye into optical grades, selecting the eye for high-definition eyeglasses, identifying amblyopia or macular diseases, or choosing an objective refraction for vision correction.