Lisa C Krause

US Patent:

6983456, Jan 3, 2006

Filed:

Oct 31, 2002

Appl. No.:

10/285299

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US
Lisa Krause - Minneapolis MN, US
Jon Steidel - Minneapolis MN, US
David Barker - Salinas CA, US
Jeffrey Paul Brooks - St. Louis MN, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/44

US Classification:

717133, 717132, 717156

Abstract:

A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

US Patent:

7703085, Apr 20, 2010

Filed:

Oct 4, 2005

Appl. No.:

11/243498

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US
Lisa Krause - Minneapolis MN, US
Jon Steidel - Minneapolis MN, US
David Barker - Salinas CA, US
Jeffrey Paul Brooks - St. Louis MN, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/45
G00O 9/44

US Classification:

717140, 717141, 717154

Abstract:

A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

US Patent:

20040088666, May 6, 2004

Filed:

Oct 31, 2002

Appl. No.:

10/285298

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US
Lisa Krause - Minneapolis MN, US
Jon Steidel - Minneapolis MN, US

International Classification:

G06F017/50

US Classification:

716/007000

Abstract:

An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into twp or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.