Loc Hoang

US Patent:

6420753, Jul 16, 2002

Filed:

Jun 30, 1997

Appl. No.:

08/884827

Inventors:

Loc B. Hoang - San Jose CA

Assignee:

Winbond Memory Laboratory - San Jose CA

International Classification:

H01L 29788

US Classification:

257321, 257315, 257316

Abstract:

A memory cell comprised of three regions of a first-type deposited on a substrate of a second-type, a first insulating layer deposited over the substrate, a floating gate disposed over the first insulating layer, a second insulating layer disposed over the floating gate and the first insulating layer, a control gate disposed over the second insulating layer and partially extending over the floating gate, and a select gate disposed over the second insulating layer. The memory cell can be configured in four different ways. When placed in a memory array, a predefined number of memory cells can be grouped into blocks. By using a byte(block)-select transistor, the memory cells can be accessed and altered on block by block basis. The novel memory cells can be manufactured without requiring additional processing steps aside from those required in the manufacturing of the comparable flash memory cells.

US Patent:

6456539, Sep 24, 2002

Filed:

Jul 12, 2001

Appl. No.:

09/903919

Inventors:

Sang Thanh Nguyen - Union City CA
Loc B. Hoang - San Jose CA
Hung Q. Nguyen - Fremont CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

36518907, 3651852, 36518521, 36518905, 365207

Abstract:

The present invention assures that valid and correct sensed data is latched before outputting from the memory device. The valid or correct sensed data is determined by the reference signal being first compared to two margin reference signals prior to latching the output of the comparator between the reference signal and the sensed signal from the selected memory cell. This maximizes the performance of the read operation as well as ensures the correct valid sense data is latched.

US Patent:

6639842, Oct 28, 2003

Filed:

May 15, 2002

Appl. No.:

10/147959

Inventors:

Loc B. Hoang - San Jose CA
Hung Q. Nguyen - Fremont CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 1600

US Classification:

36518528, 36518502, 36518525

Abstract:

A method and apparatus are disclosed which counteract coupling effects during programming of non-volatile memory cells in an array of the type which includes bit lines, word lines, and source lines, and temporary storage circuits which can be set to supply a desired state for use in connection with operations involving designated non-volatile memory cells, wherein each of the temporary storage circuits communicates with different groupings of the non-volatile memory cells by way of associated word and source lines. The method and apparatus includes precharging unselected bit lines to a program inhibit level, at a rate which is selected to reduce coupling effects between the unselected bits lines and word lines or source lines, as a part of a programming operation, inhibiting the operation of the temporary storage circuits during a first portion of the precharging step, arranging the temporary storage circuits to be responsive to a minimum number of word lines associated with the selected sector during a period in which unselected bit lines are precharged, setting ones of the temporary storage circuits to desired states following the first portion of the precharging step, and thereafter programming selected non-volatile memory cells.

US Patent:

6643174, Nov 4, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/028059

Inventors:

Loc B. Hoang - San Jose CA

Assignee:

Winbond Electronics Corporation

International Classification:

G11C 1604

US Classification:

36518511, 36523003

Abstract:

A flash electrically-erasable, programmable read-only memory (EEPROM) has multiple source lines and source line select transistors. Each group of memory cells in the EEPROM is associated with one of the source line select transistors. Each source line is associated with more than one group of memory cells. When one group of memory cells is to be programmed, a relatively high voltage is coupled to its corresponding source line. Its corresponding source line select transistor then couples the source line to the group of memory cells to be programmed. In this manner, only the group to be programmed is exposed to the high voltage. This decreases the amount of high voltage stress placed on the other memory cells and increases the reliability and lifetime of the EEPROM.

US Patent:

6687162, Feb 3, 2004

Filed:

Apr 19, 2002

Appl. No.:

10/126450

Inventors:

Sheng-Hsiung Hsueh - San Jose CA
Ganshu Ben Lee - Santa Clara CA
Loc Bao Hoang - San Jose CA
Albert V. Kordesch - San Jose CA

Assignee:

Winbond Electronics Corporation - Hsin Chu

International Classification:

G11C 1606

US Classification:

36518521, 3651852

Abstract:

Techniques to more accurately read values stored in data cells. In an aspect, one reference cell is provided for each group of data cells having similar configuration (e. g. , similar layout and orientation). For split-gate memory cells arranged in pairs, each pair includes two data cells implemented as mirrored image of one another. Two reference cells may then be used, one reference cell for each data cell in a pair. In another aspect, the data paths for the reference and data cells for read operation are matched. This matching may be achieved by using the same circuit design for the data and reference sense amplifiers, using the same layout and orientation for the sense amplifiers, matching the lines for the two data paths, matching the structure (e. g. , length and width) and the diffusion region (e. g. , doping concentration and contact) for the sense amplifiers and lines, and so on.

US Patent:

6697281, Feb 24, 2004

Filed:

Nov 8, 2001

Appl. No.:

10/010617

Inventors:

Loc B. Hoang - San Jose CA

Assignee:

Winbond Electronics Corporation

International Classification:

G11C 1604

US Classification:

36518517, 36518511, 36518529

Abstract:

A flash electrically-erasable, programmable read-only memory (EEPROM) with reduced area. The memory cells of the EEPROM are arranged into groups, and access to the groups is controlled by select transistors. In this manner the number of select transistors is reduced without requiring the entire array to be programmed or erased.

US Patent:

6788595, Sep 7, 2004

Filed:

Aug 5, 2002

Appl. No.:

10/213243

Inventors:

Hung Q. Nguyen - Fremont CA
Sang Thanh Nguyen - Union City CA
Loc B. Hoang - San Jose CA
Tam M. Nguyen - San Jose CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

365200, 365201

Abstract:

Predetermined data is stored in first and second predetermined locations of a memory. The first location may be in a first part of the memory, and the second location may be in a redundant part of the memory. At power up or reset, the first predetermined location of the memory successively is read and compared to data stored in a register until the comparison indicates a match for a predefined number of consecutive reads and comparisons. The successive reading may be stopped if the number of comparisons indicating a failure equals another predefined number of times. The data stored in the second predetermined location also is read. This data may be compared to the data previously read from the second predetermined location. The reading and comparing from the first predetermined location and the reading from the second predetermined location are continued until the number of times data is read from the second predetermined location equals a third predetermined number. The voltage signal is then determined to be valid after sufficient successive reads of the first predetermined location of the memory.

US Patent:

6839277, Jan 4, 2005

Filed:

Sep 17, 2002

Appl. No.:

10/246196

Inventors:

Hung Q. Nguyen - Fremont CA, US
Loc B. Hoang - San Jose CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518504, 36518904

Abstract:

A memory system includes manufacturer identifiers, such as serial numbers and part numbers, stored in locations of memory that are unalterable by end users. A customer identification location of the memory allows the user to program its own identifier and includes a locking code that prevents subsequent alteration of the customer identification location. A recall procedure at power on verifies the content of the locked code for allowing alteration of the memory.