Loc Duc Hoang

US Patent:

6456539, Sep 24, 2002

Filed:

Jul 12, 2001

Appl. No.:

09/903919

Inventors:

Sang Thanh Nguyen - Union City CA
Loc B. Hoang - San Jose CA
Hung Q. Nguyen - Fremont CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

36518907, 3651852, 36518521, 36518905, 365207

Abstract:

The present invention assures that valid and correct sensed data is latched before outputting from the memory device. The valid or correct sensed data is determined by the reference signal being first compared to two margin reference signals prior to latching the output of the comparator between the reference signal and the sensed signal from the selected memory cell. This maximizes the performance of the read operation as well as ensures the correct valid sense data is latched.

US Patent:

6788595, Sep 7, 2004

Filed:

Aug 5, 2002

Appl. No.:

10/213243

Inventors:

Hung Q. Nguyen - Fremont CA
Sang Thanh Nguyen - Union City CA
Loc B. Hoang - San Jose CA
Tam M. Nguyen - San Jose CA

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

365200, 365201

Abstract:

Predetermined data is stored in first and second predetermined locations of a memory. The first location may be in a first part of the memory, and the second location may be in a redundant part of the memory. At power up or reset, the first predetermined location of the memory successively is read and compared to data stored in a register until the comparison indicates a match for a predefined number of consecutive reads and comparisons. The successive reading may be stopped if the number of comparisons indicating a failure equals another predefined number of times. The data stored in the second predetermined location also is read. This data may be compared to the data previously read from the second predetermined location. The reading and comparing from the first predetermined location and the reading from the second predetermined location are continued until the number of times data is read from the second predetermined location equals a third predetermined number. The voltage signal is then determined to be valid after sufficient successive reads of the first predetermined location of the memory.

US Patent:

6839277, Jan 4, 2005

Filed:

Sep 17, 2002

Appl. No.:

10/246196

Inventors:

Hung Q. Nguyen - Fremont CA, US
Loc B. Hoang - San Jose CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518504, 36518904

Abstract:

A memory system includes manufacturer identifiers, such as serial numbers and part numbers, stored in locations of memory that are unalterable by end users. A customer identification location of the memory allows the user to program its own identifier and includes a locking code that prevents subsequent alteration of the customer identification location. A recall procedure at power on verifies the content of the locked code for allowing alteration of the memory.

US Patent:

6876031, Apr 5, 2005

Filed:

Feb 23, 1999

Appl. No.:

09/256265

Inventors:

Dah-Bin Kao - Palo Alto CA, US
Loc B. Hoang - San Jose CA, US
Albert T. Wu - Palo Alto CA, US

Assignee:

Winbond Electronics Corporation - Hsin chu

International Classification:

H01L029/788
G11C016/04

US Classification:

257315, 257317, 36518501, 36518526, 36518529

Abstract:

A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

US Patent:

6972994, Dec 6, 2005

Filed:

Mar 9, 2004

Appl. No.:

10/797156

Inventors:

Hung Q. Nguyen - Fremont CA, US
Steve Choi - Irvine CA, US
Loc Hoang - San Jose CA, US
Alexander Kotov - Sunnyvale CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C016/06
G11C029/00

US Classification:

36518509, 365200

Abstract:

A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.

US Patent:

20020102774, Aug 1, 2002

Filed:

Oct 18, 2001

Appl. No.:

10/035727

Inventors:

Dah-Bin Kao - Palo Alto CA, US
Loc Hoang - San Jose CA, US
Albert Wu - Palo Alto CA, US

International Classification:

H01L021/335

US Classification:

438/142000

Abstract:

A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.

US Patent:

59034874, May 11, 1999

Filed:

Nov 25, 1997

Appl. No.:

8/978157

Inventors:

Albert T. Wu - Palo Alto CA
Dah-Bin Kao - Palo Alto CA
Loc B. Hoang - San Jose CA

Assignee:

Windbond Electronics Corporation - Taiwan

International Classification:

G11C27/00

US Classification:

365 45

Abstract:

An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

US Patent:

62115472, Apr 3, 2001

Filed:

Nov 24, 1997

Appl. No.:

8/976751

Inventors:

Dah-Bin Kao - Palo Alto CA
Loc B. Hoang - San Jose CA
Albert T. Wu - Palo Alto CA

Assignee:

Winbond Electronics Corporation - Hsin Chu

International Classification:

H01L 29788
G11C 1604

US Classification:

257317

Abstract:

A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.