Loc V Nguyen

US Patent:

6362653, Mar 26, 2002

Filed:

Feb 6, 2001

Appl. No.:

09/777286

Inventors:

Joseph M. Milewski - Endicott NY
Loc K. Nguyen - Essex Junction VT
Douglas W. Stout - Milton VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1716

US Classification:

326 81, 326 83, 326 57

Abstract:

A high voltage tolerant receiver that matches a voltage drop across an NFET pass-gate at the input to the receiver with a voltage drop across a semiconductor device, formatted as a diode, and connected between an input stage and an input stage voltage supply source.

US Patent:

6441670, Aug 27, 2002

Filed:

Aug 15, 2001

Appl. No.:

09/930413

Inventors:

Joseph M. Milewski - Endicott NY
Akio Miyoshi - Ohtsuy, JP
Loc Khac Nguyen - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 508

US Classification:

327323, 326 80

Abstract:

Receiver circuit providing interface between a legacy system sourcing logic signals including high logic level signals at first voltage levels to semiconductor IC devices operating at second voltage levels, wherein the first voltage levels are greater than the second voltage levels. The receiver circuit comprises: a pass gate device receiving the input voltages including high level logic signals at first logic levels and translating the high logic level signals to an intermediate voltage level for output at a first circuit node, the intermediate voltage level being less than the first voltage level; a first inverter device for receiving the translated voltages at the intermediate voltage levels and inverting the voltages for output at a second circuit node, whereby high input logic level voltages are pulled down at the second node and low input logic level voltages are pulled up at the second node; a circuit element in series with the first inverter device for connecting the first inverter device to a voltage supply source that provides pulled up signals at the second voltage levels in response to low logic level input voltages; and, a circuit responsive to pulled down voltage at the second node for deactivating the first circuit element to thereby prevent leakage current to ground through the first inverter device. Stable switching of voltages is achieved at the second node in a manner that eliminates leakage current between the voltage supply source providing pulled up signals at the second voltage levels and the receiver input.