Louis V Rodriguez

US Patent:

54189365, May 23, 1995

Filed:

Jul 5, 1994

Appl. No.:

8/277933

Inventors:

Louis Rodriguez - Dallas TX
Kevin E. Deierling - Dallas TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

G06F 1300

US Classification:

395550

Abstract:

A low-power timekeeping integrated circuit, using a double-buffered memory architecture: The user can freely read from user memory at any time, and an internal clock periodically updates a set of timekeeping registers. Transfer from the timekeeping registers to user memory (for update of the data) is performed as a block transfer, asynchronously and invisibly to the user. A special timing-window requirement is used to avoid access collision problems: each edge of the one-hertz oscillator signal is delayed slightly, and it is the delayed signal which actually clocks the update to the timekeeping registers. After a further small delay (long enough to allow for worst-case ripple-through delays in the timekeeping registers), a latched signal (NO. sub. -- RIPPLE, in the presently preferred embodiment) is driven active. The signal NO. sub.

US Patent:

51480514, Sep 15, 1992

Filed:

Dec 14, 1990

Appl. No.:

7/628693

Inventors:

Kevin E. Deierling - Dallas TX
Louis Rodriguez - Dallas TX

Assignee:

Dallas Semiconductor Corporation - Dallas TX

International Classification:

H03K 1720

US Classification:

3072723

Abstract:

An integrated circuit with power-up-warning circuitry wherein time integration and voltage level testing are done sequentially instead of simultaneously. A reference voltage is generated by current sourced to a reference voltage circuit, and this reference voltage is used as follows: An inverter receives the reference voltage as an input, and switches when the power supply becomes high enough that the reference voltage appears as a "low" level. When this inverter switches, current begins to be sourced to a timing capacitor. After the timing capacitor has charged up to a predetermined level, the current source to the reference-voltage node is turned off, and the power-up-warning signal (which has been driven high by output buffers) is turned off.