Luis E Rosales

US Patent:

20200335432, Oct 22, 2020

Filed:

Apr 18, 2019

Appl. No.:

16/388136

Inventors:

- Santa Clara CA, US
Jeffory L. Smalley - East Olympia WA, US
Thomas T. Holden - Grass Valley CA, US
Silver A. Estrada Rodriguez - Zapopan, MX
Luis E. Rosales Galvan - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/498
H01L 21/67
H05K 1/18

Abstract:

A circuit board assembly includes at least one circuit board having a plurality of conductive layers, the at least one circuit board having a first face and an opposite second face. A first chip socket on the first face is positioned opposite of a second chip socket on the second face. In one example, each chip socket can receive a processor. The first and second chip sockets may be arranged in a mirrored fashion with respect to one another, or an overlapping but non-mirrored fashion. In any such arrangements, as fasteners are tightened to fully seat first and second chips respectively installed in the first and second chip sockets, forces applied to the first chip effectively neutralize or otherwise reduce opposing forces applied to the second chip, thereby reducing circuit board deflection.