Mahesh N Mamidipaka

US Patent:

7750680, Jul 6, 2010

Filed:

Dec 7, 2007

Appl. No.:

11/952937

Inventors:

Mahesh Mamidipaka - Santa Clara CA, US

Assignee:

Apache Design Solutions, Inc. - San Jose CA

International Classification:

H03K 19/00

US Classification:

326 93, 326 95, 326 98

Abstract:

A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.

US Patent:

20070024318, Feb 1, 2007

Filed:

Jul 29, 2005

Appl. No.:

11/193149

Inventors:

Mahesh Mamidipaka - Santa Clara CA, US

International Classification:

H03K 19/173

US Classification:

326038000

Abstract:

A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.