Majid M Mansoori

US Patent:

6828213, Dec 7, 2004

Filed:

Feb 28, 2003

Appl. No.:

10/376021

Inventors:

Freidoon Mehrad - Plano TX
Zhihao Chen - Plano TX
Majid M. Mansoori - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

438435

Abstract:

A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.

US Patent:

6830980, Dec 14, 2004

Filed:

Mar 20, 2003

Appl. No.:

10/393419

Inventors:

Majid Movahed Mansoori - Plano TX
Donald S. Miles - Plano TX
Srinivasan Chakravarthi - Richardson TX
P R Chidambaram - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438308

Abstract:

Semiconductor device fabrication methods are provided in which a carbon-containing region is formed in a wafer to inhibit diffusion of dopants during fabrication. Front-end thermal processing operations, such as oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.

US Patent:

6872610, Mar 29, 2005

Filed:

Nov 18, 2003

Appl. No.:

10/716025

Inventors:

Majid M. Mansoori - Plano TX, US
Zhigiang Wu - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/336

US Classification:

438197

Abstract:

Methods are presented, in which an oxide protection layer is provided on a gate structure for protection against poly mushrooming during selective epitaxial silicon deposition in fabricating elevated or recessed source transistors. In one implementation, the protection layer is constructed by depositing silicon germanium over a gate polysilicon layer prior to gate patterning, and oxidizing the device to form a silicon germanium oxide over the gate polysilicon. The protection layer is then removed following selective epitaxial deposition.

US Patent:

7109556, Sep 19, 2006

Filed:

Nov 16, 2004

Appl. No.:

10/989480

Inventors:

Majid M. Mansoori - Plano TX, US
Christoph Wasshuber - Cambridge MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/76
H01L 29/94

US Classification:

257384, 257754

Abstract:

The present invention provides source/drain electrode for a transistor. The source/drain electrode comprises a plurality of polysilicon grains located over a source/drain region. A metal salicide layer conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the above described source/drain electrode , and integrated circuit have includes a semiconductor device having the described source/drain electrodes.

US Patent:

7199011, Apr 3, 2007

Filed:

Jul 16, 2003

Appl. No.:

10/620492

Inventors:

Majid Movahed Mansoori - Plano TX, US
Alwin Tsao - Garland TX, US
Antonio Luis Pacheco Rotondaro - Dallas TX, US
Brian Ashley Smith - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438270, 438299, 438303, 257E21092, 257E21115

Abstract:

The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.

US Patent:

7344951, Mar 18, 2008

Filed:

Sep 13, 2004

Appl. No.:

10/939862

Inventors:

Patricia B. Smith - Colleyville TX, US
Majid M. Mansoori - Plano TX, US
Shirin Siddiqui - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438300, 438270, 438278, 438301, 438305, 257E21431

Abstract:

According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.

US Patent:

7427543, Sep 23, 2008

Filed:

Aug 7, 2006

Appl. No.:

11/462914

Inventors:

Majid M. Mansoori - Dallas TX, US
Christoph A. Wasshuber - Cambridge MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438647, 438652

Abstract:

The present invention provides source/drain electrode for a transistor. The source/drain electrode comprises a plurality of polysilicon grains located over a source/drain region. A metal salicide layer conformally coats the plurality of polysilicon grains. The present invention also includes a method of fabricating the above described source/drain electrode , and integrated circuit have includes a semiconductor device having the described source/drain electrodes.

US Patent:

7892931, Feb 22, 2011

Filed:

Dec 20, 2006

Appl. No.:

11/613798

Inventors:

Seetharaman Sridhar - Richardson TX, US
Majid Mansoori - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438300, 257E21431, 257E21437, 257E21632, 438199

Abstract:

A method for forming a transistor's drain extension and recessed strained epi regions with a single mask step. In an example embodiment, the method may include forming a patterned photoresist layer over a protection layer in a NMOS region and then etching exposed portions of the protection layer in the PMOS region to form extension sidewalls on the transistors in the PMOS region plus a protective hardmask over the NMOS region. The method may further include forming the extension regions for the PMOS region transistors , performing a recess etch of active regions of the PMOS region transistors , and forming the recessed strained epi regions.