Man Man Trinh

US Patent:

6604136, Aug 5, 2003

Filed:

Jun 25, 1999

Appl. No.:

09/337025

Inventors:

Chi-Hua Chang - Milpitas CA
Man Dieu Trinh - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15173

US Classification:

709223, 709229

Abstract:

The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.

US Patent:

6708210, Mar 16, 2004

Filed:

Mar 13, 2003

Appl. No.:

10/389634

Inventors:

Chi-Hua Chang - Milpitas CA
Man Dieu Trinh - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15173

US Classification:

709223, 709229

Abstract:

The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.

US Patent:

6724767, Apr 20, 2004

Filed:

Mar 16, 1999

Appl. No.:

09/271061

Inventors:

Simon Chong - Fremont CA
Anguo Tony Huang - Mountain View CA
Man Dieu Trinh - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 1228

US Classification:

370412, 370413, 709238, 710 52

Abstract:

Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission. A VC descriptor for each VC keeps track of the memory locations of the next packet descriptor and the next buffer descriptor to be de-queued, and the memory locations for storing the next packet descriptors and the next buffer descriptors to be queued.

US Patent:

6996117, Feb 7, 2006

Filed:

Sep 19, 2002

Appl. No.:

10/251946

Inventors:

Barry Lee - Union City CA, US
Man Dieu Trinh - San Jose CA, US
Ryszard Bleszynski - Saratoga CA, US

Assignee:

Bay Microsystems, Inc. - San Jose CA

International Classification:

H04L 12/54

US Classification:

370429, 370412, 370465

Abstract:

An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i. e. , the time to complete a process is known) and that it employs a pipelined “multiple instruction single date” (“MISD”) architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.

US Patent:

7349403, Mar 25, 2008

Filed:

Sep 19, 2002

Appl. No.:

10/251325

Inventors:

Barry Lee - Union City CA, US
Man Dieu Trinh - San Jose CA, US

Assignee:

Bay Microsystems, Inc. - San Jose CA

International Classification:

H04L 12/28

US Classification:

37039521, 3703955

Abstract:

A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.

US Patent:

7411968, Aug 12, 2008

Filed:

Aug 7, 2003

Appl. No.:

10/637723

Inventors:

Simon Chong - Fremont CA, US
Anguo Tony Huang - Mountain View CA, US
Man Dieu Trinh - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

370412, 37039572

Abstract:

Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission. A VC descriptor for each VC keeps track of the memory locations of the next packet descriptor and the next buffer descriptor to be de-queued, and the memory locations for storing the next packet descriptors and the next buffer descriptors to be queued.

US Patent:

63112124, Oct 30, 2001

Filed:

Mar 16, 1999

Appl. No.:

9/270287

Inventors:

Simon Chong - Fremont CA
David A. Stelliga - Pleasanton CA
Ryszard Bleszynski - Cupertino CA
Anguo Tony Huang - Mountain View CA
Man Dieu Trinh - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15167

US Classification:

709212

Abstract:

Systems and methods for storing, or caching, VC descriptors on a single-chip network processor to enhance system performance. The single-chip network processor includes an on-chip cache memory that stores VC descriptors for fast retrieval. When a VC descriptor is to be retrieved, a processing engine sends a VC descriptor identifier to a content-addressable memory (CAM), which stores VC descriptor identifiers in association with addresses in the cache where associated VC descriptors are stored. If the desired VC descriptor is stored in the cache, the CAM returns the associated address to the processing engine and the processing engine retrieves the VC descriptor from the cache memory. If the VC descriptor is not stored in the cache, the CAM returns a miss signal to the processing engine, and the processing engine retrieves the VC descriptor from an off-chip memory. In this manner, VC descriptors associated with high bandwidth VCs are stored to the cache and retrieved much quicker from the cache than from the off-chip memory.