Uc Irvine Jan 1, 1992 - 1994
Masters, Master of Science In Electrical Engineering
The Collins College of Hospitality Management at Cal Poly Pomona Jan 1, 1989 - 1992
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Device Drivers Asic Soc Network Processors Ethernet Embedded Systems Debugging Verilog Vxworks Arm Embedded Software
Chi-Hua Chang - Milpitas CA Man Dieu Trinh - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15173
US Classification:
709223, 709229
Abstract:
The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.
Application Programming Interfaces And Methods Enabling A Host To Interface With A Network Processor
Chi-Hua Chang - Milpitas CA Man Dieu Trinh - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15173
US Classification:
709223, 709229
Abstract:
The present invention provides application programming interfaces (APIs) which allow a host to control the functioning of a network processor and also perform various network data manipulation functions. The APIs are intended to encapsulate as much as possible the underlying messaging between the host system and the network processor and to hide the low device level command details from the host. The APIs are provided by a program module. A host may invoke an API which is then communicated by the program module to the network processor where functions corresponding to the API are performed. Responses to the APIs may be forwarded back to the host. Asynchronous callback functions, invoked in response to the API calls, may be used to forward responses to the host.
Two-Dimensional Queuing/De-Queuing Methods And Systems For Implementing The Same
Simon Chong - Fremont CA Anguo Tony Huang - Mountain View CA Man Dieu Trinh - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 1228
US Classification:
370412, 370413, 709238, 710 52
Abstract:
Systems and methods for queuing and de-queuing packets in a two-dimensional link list data structure. A network processor processes data for transmission for a plurality of Virtual Connections (VCs). The processor creates a two-dimensional link list data structure for each VC. The data field of each data packet is stored in one or more buffer memories. Each buffer memory has an associated buffer descriptor that includes a pointer to the location of the buffer memory, and a pointer pointing to the memory of the next buffer descriptor associated with a buffer memory storing data for the same packet. Each data packet also has an associated packet descriptor including a pointer pointing to the memory location of the first buffer descriptor associated with that packet, and a pointer pointing to the memory location of the packet descriptor associated with the next data packet queued for transmission. A VC descriptor for each VC keeps track of the memory locations of the next packet descriptor and the next buffer descriptor to be de-queued, and the memory locations for storing the next packet descriptors and the next buffer descriptors to be queued.
Method And Apparatus For Issuing Commands To A Network Processor Configured To Provide A Plurality Of Apis
Man Dieu Trinh - San Jose CA Chi-Hua Chang - Milpitas CA Srinivas Dabir - Saratoga CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1516
US Classification:
719328, 709229
Abstract:
The present invention provides techniques for controlling the functionality of a network processor and for facilitating integration of the network processor with a host system. Application programming interfaces (APIs) are provided which can be invoked by the host system for performing device level functions on the network processor. The APIs are provided by a device control module which may execute either on the host system or on the network processor. A host application may invoke an API and the function corresponding to the invoked API is performed by the network processor. Responses or results from the function execution may then be forwarded by the network processor to the host application.
Vertical Instruction And Data Processing In A Network Processor Architecture
Barry Lee - Union City CA, US Man Dieu Trinh - San Jose CA, US Ryszard Bleszynski - Saratoga CA, US
Assignee:
Bay Microsystems, Inc. - San Jose CA
International Classification:
H04L 12/54
US Classification:
370429, 370412, 370465
Abstract:
An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i. e. , the time to complete a process is known) and that it employs a pipelined “multiple instruction single date” (“MISD”) architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.
Memory Management System And Algorithm For Network Processor Architecture
Ryszard Bleszynski - Saratoga CA, US Man D. Trinh - San Jose CA, US
Assignee:
Bay Microsystems, Inc. - San Jose CA
International Classification:
H04L 12/56
US Classification:
37039572, 711153, 710 28
Abstract:
An embodiment of this invention pertains to a system and method for balancing memory accesses to a low cost memory unit in order to sustain and guarantee a desired line rate regardless of the incoming traffic pattern. The memory unit may include, for example, a group of dynamic random access memory units. The memory unit is divided into memory channels and each of the memory channels is further divided into memory lines, each of the memory lines includes one or more buffers that correspond to the memory channels. The determination as to which of one or more buffers within a memory line an incoming information element is stored is based on factors such as the number of buffers pending to be read within each of the memory channels, the number of buffers pending to be written within each of the memory channels, and the number of buffers within each of the memory channels that has data written to it and is waiting to be read.
Man D. Trinh - San Jose CA, US Ryzsard Bleszynski - Saratoga CA, US Barry T. Lee - Union City CA, US Steve C. Chen - Cupertino CA, US Eric K. Yang - Los Altos CA, US Simon S. Chong - Fremont CA, US Tony J. Chiang - Fremont CA, US Jun-Wen Tsong - San Jose CA, US Goichiro Ono - San Jose CA, US Charles F. Gershman - Pleasanton CA, US
Assignee:
Bay Microsystems, Inc. - San Jose CA
International Classification:
H04L 12/54
US Classification:
370428, 370419, 370463
Abstract:
A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service (“QoS”). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.
Barry Lee - Union City CA, US Man Dieu Trinh - San Jose CA, US
Assignee:
Bay Microsystems, Inc. - San Jose CA
International Classification:
H04L 12/28
US Classification:
37039521, 3703955
Abstract:
A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.
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