Man Wang

US Patent:

6977521, Dec 20, 2005

Filed:

Apr 19, 2005

Appl. No.:

11/109966

Inventors:

Man Wang - Sunnyvale CA, US

Assignee:

KLP International, Ltd. - Santa Clara CA

International Classification:

H03K019/177

US Classification:

326 41, 326 38

Abstract:

A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that can perform combinatorial logic. The logic head can further be fractured into two independent logical units.

US Patent:

7061275, Jun 13, 2006

Filed:

Oct 17, 2005

Appl. No.:

11/252126

Inventors:

Man Wang - Sunnyvale CA, US

Assignee:

KLP International, Ltd. - Santa Clara CA

International Classification:

H03K 19/094
H03K 17/693

US Classification:

326113, 326 38, 326106, 327408

Abstract:

A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that can perform combinatorial logic. The logic head can further be fractured into two independent logical units.

US Patent:

7193436, Mar 20, 2007

Filed:

Apr 18, 2005

Appl. No.:

11/108927

Inventors:

Man Wang - Sunnyvale CA, US
Suhail Zain - San Ramon CA, US

Assignee:

KLP International Ltd. - Santa Clara CA

International Classification:

G06F 7/38
H03K 19/177

US Classification:

326 40, 326 38, 326 41

Abstract:

The described embodiments relate to the general area of Field Programmable Gate Arrays (FPGAs), and, in particular, to the architecture and the structure of the building blocks of the FPGAs. Proposed logic units, as separate units or a chain of units, which are mainly comprised of look-up tables, multiplexers, and latches, implement different mathematical and logical functions. Having two outputs, the embodiments of the logic unit can operate in a split mode and perform two separate logic and/or arithmetic functions at the same time. Chains of the proposed logic units, wherein every other unit is clocked by one of the two half clock cycles and utilizes local interconnections instead of traditional routing channels, add to efficiency and speed, and reduce required real estate.

US Patent:

7816947, Oct 19, 2010

Filed:

Mar 31, 2008

Appl. No.:

12/059509

Inventors:

Man Wang - Saratoga CA, US

International Classification:

H03K 19/173
H03K 19/20
H03K 19/094

US Classification:

326 50, 326 49, 326122

Abstract:

A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

US Patent:

7969188, Jun 28, 2011

Filed:

Sep 13, 2010

Appl. No.:

12/880522

Inventors:

Man Wang - Saratoga CA, US

International Classification:

H03K 19/173
H03K 19/20
H03K 19/094

US Classification:

326 49, 326 38, 36518514

Abstract:

A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

US Patent:

8274310, Sep 25, 2012

Filed:

May 23, 2011

Appl. No.:

13/113748

Inventors:

Man Wang - Saratoga CA, US

International Classification:

H03K 19/173
H03K 19/20
H03K 19/094

US Classification:

326 49, 326 38, 36518514

Abstract:

A method and apparatus of providing a programmable system using non-volatile programmable transistors are disclosed. A programmable logic circuit, in one embodiment, includes a first programmable transistor and a second programmable transistor. The first programmable transistor includes a first gate terminal, a first source terminal, a first drain terminal, and a first programming terminal. The second programmable transistor includes a second gate terminal, a second source terminal, and a second drain terminal, and a second programmable terminal. The first and second programmable transistors include non-volatile memory elements. The first and the second gate terminals are coupled to an input terminal, and the first drain terminal and the second source terminal are coupled to an output terminal to perform a logic function.

US Patent:

20050035783, Feb 17, 2005

Filed:

Aug 15, 2003

Appl. No.:

10/642370

Inventors:

Man Wang - Sunnyvale CA, US

International Classification:

H03K019/177

US Classification:

326039000

Abstract:

A field programmable gate array (FPGA) having hierarchical interconnect structure is disclosed. The FPGA includes logic heads that have signals routed therebetween by the interconnect structure. Each logic head includes a plurality of cascadable logic blocks that can perform combinatorial logic. The logic head can further be fractured into two independent logical units.

US Patent:

20050218929, Oct 6, 2005

Filed:

Jul 2, 2004

Appl. No.:

10/883901

Inventors:

Man Wang - Sunnyvale CA, US
Jack Peng - San Jose CA, US

International Classification:

H03K019/177

US Classification:

326041000

Abstract:

The present invention relates to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic cells offer, among other advantages, by-pass and feedback paths, fewer transistors, no need for dedicated carry logic or multiple registers, 3-input instead of 4-input look-up tables, easy implementation of up to 4-input logic functions, and multiplication.