Manish Gupta

US Patent:

6381738, Apr 30, 2002

Filed:

Jul 16, 1999

Appl. No.:

09/354140

Inventors:

Manish Gupta - Peekskill NY
Mauricio J. Serrano - San Jose CA
Vugranam C. Sreedhar - Whiteplains NY
Samuel Pratt Midkiff - Upper Saddle River NJ

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 945

US Classification:

717 8, 717 4, 717 5, 717 7, 717 9, 717136, 717162, 717124, 717140, 706206, 709196

Abstract:

Information is computed about the reachability relationships among objects and pointers to enable transformation of a computer program for optimizing the creation and destruction of objects, while strictly performing the semantics of the original program. An interprocedural analysis is used to determine whether an object that is allocated on the heap during the execution of a procedure is not reachable from any global variable, parameter, or the return value of the procedure after it returns. If so, that object can be allocated on the stack frame of the procedure in which it is otherwise heap-allocated. This simplifies the memory allocation and deallocation operations, as allocation on the stack can be done more efficiently than allocation on the heap, and objects allocated on the stack frame of a procedure are automatically deallocated when the procedure returns, without incurring the overhead of garbage collection. This, in turn, leads to faster programs which use fewer computer processor resources to execute. The interprocedural analysis of the program summarizes the effect of a procedure call succinctly for different calling contexts of the procedure using a single summary representation.

US Patent:

6487716, Nov 26, 2002

Filed:

Oct 8, 1999

Appl. No.:

09/415137

Inventors:

Manish Gupta - Peekskill NY
Michael Hind - Cortlandt Manor NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 944

US Classification:

717159, 717147, 717148, 712244

Abstract:

A method and several variants are provided for analyzing and transforming a computer program such that instructions may be reordered even across instructions that may throw an exception, while strictly preserving the precise exception semantics of the original program. The method uses program analysis to identify the subset of program state that needs to be preserved if an exception is thrown. Furthermore, the method performs a program transformation that allows dependence constraints among potentially excepting instructions to be completely ignored while applying program optimizations. This transformation does not require any special hardware support, and requires a compensation code to be executed only if an exception is thrown, i. e. , no additional instructions need to be executed if an exception is not thrown. Variants of the method show how one or several of the features of the method may be performed.

US Patent:

6530079, Mar 4, 2003

Filed:

Jun 2, 1999

Appl. No.:

09/323989

Inventors:

Manish Gupta - Peekskill NY
Mauricio J. Serrano - San Jose CA
Vugranam C. Sreedhar - Whiteplains NY
Samuel Pratt Midkiff - Upper Saddle River NJ

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9445

US Classification:

717158, 717127, 717128, 717129, 717130, 717131, 717152, 717153, 717157, 717159, 712227

Abstract:

A method and several variants for using information about the scope of access of objects acted upon by mutual exclusion, or mutex, locks to transform a computer program by eliminating locking operations from the program or simplifying the locking operations, while strictly performing the semantics of the original program. In particular, if it can be determined by a compiler that the object locked can only be accessed by a single thread it is not necessary to perform the âacquireâ or âreleaseâ part of the locking operation, and only its side effects must be performed. Likewise, if it can be determined that the side effects of a locking operation acting on a variable which is locked in multiple threads are not needed, then only the locking operation, and not the side effects, needs to be performed. This simplifies the locking operation, and leads to faster programs which use fewer computer processor resources to execute; and programs which perform fewer shared memory accesses, which in turn not only causes the optimized program, but also other programs executing on the same computing machine to execute faster. The method also describes how information about the semantics of the locking operation side effects and the information about the scope of access can also be used to eliminate performing the side effect parts of the locking operation, thereby completely eliminating the locking operation.

US Patent:

6643741, Nov 4, 2003

Filed:

Aug 10, 2000

Appl. No.:

09/636048

Inventors:

Yefim Shuf - Forest Hills NY
Hubertus Franke - Courtlandt Manor NY
Manish Gupta - Peekskill NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1206

US Classification:

711135, 711156, 711141

Abstract:

The invention teaches how to reduce the traffic associated with handling cache lines containing useless data (i. e. cache lines corresponding to pages that have been invalidated). The invention makes it possible to evict such cache lines earlier, to avoid write backs of useless data from such cache lines to main memory, and to avoid transmitting useless data from such cache lines to the requesting remote coherence controller in a multiprocessor system. The present invention describes a mechanism for invalidating cache lines containing useless data transparently and without programmers involvement. For efficiency, the content of a cache line containing useless data is invalidated only when the line is referenced or is about to be allocated for some new data.

US Patent:

6886085, Apr 26, 2005

Filed:

Aug 10, 2000

Appl. No.:

09/636049

Inventors:

Yefim Shuf - Forest Hills NY, US
Hubertus Franke - Courtlandt Manor NY, US
Manish Gupta - Peekskill NY, US
Marc Snir - Briarcliff Manor NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F012/00

US Classification:

711159, 711143, 711165, 709315

Abstract:

A method and an apparatus that improves virtual memory management. The proposed method and apparatus provides an application with an efficient channel for communicating information about future behavior of an application with respect to the use of memory and other resources to the OS, a paging daemon, and other system software. The state of hint bits, which are integrated into page table entries and TLB entries and are used for communicating information to the OS, can be changed explicitly with a special instruction or implicitly as a result of referencing the associated page. The latter is useful for canceling hints. The method and apparatus enables memory allocators, garbage collectors, and compilers (such as those used by the Java platform) to use a page-aligned heap and a page-aligned stack to assist the OS in effective management of memory resources. This mechanism can also be used in other system software.

US Patent:

6892212, May 10, 2005

Filed:

Mar 7, 2002

Appl. No.:

10/093656

Inventors:

Yefim Shuf - Forest Hills NY, US
Manish Gupta - Yorktown Heights NY, US
Rajesh Bordawekar - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B06F017/30

US Classification:

707206, 707 10

Abstract:

A computing apparatus and method classify data objects into at least a first type and alternatively a second type, and allocate a first portion of computer memory to objects of the first type and a second portion of computer memory to objects of the second type. Then the method performs garbage collection of data objects within at least one portion of computer memory while retaining surviving objects within the computer memory. Objects of the first type occur in a computer memory with a frequency that exceeds a selected threshold, and are designated “prolific. ” Objects of the second type occur in the computer memory with a frequency that does not exceed the selected threshold, and are designated “non-prolific”.

US Patent:

6973646, Dec 6, 2005

Filed:

Jul 21, 2000

Appl. No.:

09/621571

Inventors:

Rajesh Bordawekar - Yorktown Heights NY, US
Manish Gupta - Peekskill NY, US
Samuel Pratt Midkiff - Upper Saddle River NJ, US
Mauricio J. Serrano - San Jose CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/45

US Classification:

717146, 717140, 717145, 717152, 713168

Abstract:

This invention describes a method and several variants for compiling programs or components of programs in a mixed static and dynamic environment, so as to reduce the amount of time and memory spent in run-time compilation, or to exercise greater control over testing of the executable code for the program, or both. The invention involves generating persistent code images prior to program execution based on static compilation or dynamic compilation from a previous run, and then, adapting those images during program execution. We describe a method for generating auxiliary information in addition to the executable code that is recorded in the persistent code image. Further, we describe a method for checking the validity of those code images, adapting those images to the new execution context, and generating new executable code to respond to dynamic events, during program execution. Our method allows global interprocedural optimizations to be performed on the program, even if the programming language supports, or requires, dynamic binding. Variants of the method show how one or several of the features of the method may be performed.

US Patent:

7210122, Apr 24, 2007

Filed:

Mar 7, 2002

Appl. No.:

10/094019

Inventors:

Yefim Shuf - Forest Hills NY, US
Manish Gupta - Yorktown Heights NY, US
Rajesh Bordawekar - Yorktown Heights NY, US

Assignee:

International Business Machines, Corporation - Armonk NY

International Classification:

G06F 9/44
G06F 9/45
G06F 12/00
G06F 17/30

US Classification:

717116, 717152, 717140, 707206

Abstract:

A computer system and method for compiling a program, where the program executes pointer assignments from a source object to a destination object, each source object being addressable through a first pointer and each destination object being addressable through a second pointer. The system and method eliminate write barrier code from association with compiled program code when the first pointer points to a source object whose type is prolific, eliminate write barrier code from association with compiled program code when the second pointer points to a destination object whose type is non-prolific, and associate write barrier code with compiled program code when the source object is non-prolific and the destination object is prolific. Additionally, the system and method can determine not to associate write barrier code with a compiled program code if the second pointer points to a destination object whose type is non-prolific and if the first pointer points to a source object whose type is prolific.