Manish Gupta

US Patent:

6973646, Dec 6, 2005

Filed:

Jul 21, 2000

Appl. No.:

09/621571

Inventors:

Rajesh Bordawekar - Yorktown Heights NY, US
Manish Gupta - Peekskill NY, US
Samuel Pratt Midkiff - Upper Saddle River NJ, US
Mauricio J. Serrano - San Jose CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/45

US Classification:

717146, 717140, 717145, 717152, 713168

Abstract:

This invention describes a method and several variants for compiling programs or components of programs in a mixed static and dynamic environment, so as to reduce the amount of time and memory spent in run-time compilation, or to exercise greater control over testing of the executable code for the program, or both. The invention involves generating persistent code images prior to program execution based on static compilation or dynamic compilation from a previous run, and then, adapting those images during program execution. We describe a method for generating auxiliary information in addition to the executable code that is recorded in the persistent code image. Further, we describe a method for checking the validity of those code images, adapting those images to the new execution context, and generating new executable code to respond to dynamic events, during program execution. Our method allows global interprocedural optimizations to be performed on the program, even if the programming language supports, or requires, dynamic binding. Variants of the method show how one or several of the features of the method may be performed.

US Patent:

7437611, Oct 14, 2008

Filed:

Oct 21, 2004

Appl. No.:

10/968917

Inventors:

Manoj K. Agarwal - New Delhi, IN
Karen Appleby - Ossining NY, US
Manish Gupta - Elmsford NY, US
Gautam Kar - Yorktown Heights NY, US
Anindya Neogi - New Delhi, IN
Anca Sailer - Scarsdale NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 26, 714 37

Abstract:

A problem determination system and method reduces the time and effort required by system administrators to trouble shot transaction processing difficulties in a large distributed I/T environment by monitoring system component performance and computing operational performance threshold limits based on dependency graphs for the system. Using this data, a prioritized list of suspect components for the I/T system is generated.

US Patent:

7451210, Nov 11, 2008

Filed:

Nov 24, 2003

Appl. No.:

10/720300

Inventors:

Manish Gupta - Yorktown Heights NY, US
Jose E. Moreira - Yorktown Heights NY, US
Adam J. Oliner - Cheshire CT, US
Ramendra K. Sahoo - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/173

US Classification:

709224, 709223, 709226

Abstract:

A hybrid method of predicting the occurrence of future critical events in a computer cluster having a series of nodes records system performance parameters and the occurrence of past critical events. A data filter filters the logged to data to eliminate redundancies and decrease the data storage requirements of the system. Time-series models and rule based classification schemes are used to associate various system parameters with the past occurrence of critical events and predict the occurrence of future critical events. Ongoing processing jobs are migrated to nodes for which no critical events are predicted and future jobs are routed to more robust nodes.

US Patent:

7711987, May 4, 2010

Filed:

Aug 1, 2008

Appl. No.:

12/184421

Inventors:

Manoj K. Agarwal - New Delhi, IN
Karen Appleby - Ossining NY, US
Manish Gupta - Elmsford NY, US
Gautam Kar - Yorktown Heights NY, US
Anindya Neogi - New Delhi, IN
Anca Sailer - Scarsdale NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 26, 714 37

Abstract:

A problem determination system and method reduces the time and effort required by system administrators to trouble shot transaction processing difficulties in a large distributed I/T environment by monitoring system component performance and computing operational performance threshold limits based on dependency graphs for the system. Using this data, a prioritized list of suspect components for the I/T system is generated.

US Patent:

7895323, Feb 22, 2011

Filed:

Nov 10, 2008

Appl. No.:

12/267762

Inventors:

Manish Gupta - Yorktown Heights NY, US
Jose E. Moreira - Yorktown Heights NY, US
Adam J. Oliner - Cheshire CT, US
Ramendra K. Sahoo - Mohegan Lake NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/173

US Classification:

709224, 709223, 709226, 714 26, 706 15, 706 21, 706 25, 706908, 706916

Abstract:

A system for predicting an occurrence of a critical even in a computer cluster includes: a control system that includes an event log, a system parameter log, a memory for storing information related to occurrences of critical events, and a processor. The processor implements a hybrid prediction system; loads the information from the event log and the system performance log into a Bayesian network model; uses the Bayesian network model to predict a future critical event; makes future scheduling and current data migration selections; and adapts the Bayesian network model by feeding the scheduling and data migration selections.

US Patent:

7966493, Jun 21, 2011

Filed:

Dec 8, 2003

Appl. No.:

10/731623

Inventors:

Srinivasulu Puri - White Plains NY, US
Ravindra Akella - White Plains NY, US
Savita Durgada - Tarrytown NY, US
Mark Fisher - Belmont CA, US
Hany Saleeb - New Rochelle NY, US
Manish Gupta - Hartsdale NY, US
William Stearns - Manchester-by-the-Sea MA, US

Assignee:

Oracle International Corporation - Redwood City CA

International Classification:

H04L 9/32

US Classification:

713176, 713151

Abstract:

A method of and system for intercepting a transaction instantiated by a database application to determine if an electronic signature is necessary to commit the transaction to the database is disclosed. In one embodiment the method comprises calling an application program interface to raise an event in response to a triggering action generated by the database application; initiating a workflow process that executes a rule to determine if an electronic signature is required to approve the transaction; and if execution of the rule results in a determination that an electronic signature is required for the transaction, instantiating a signature collection process. Some embodiments further comprise obtaining an electronic signature in response to the signature collection process and thereafter, verifying the electronic signature and updating a filed of the electronic record to indicate a valid signature was collected if the electronic signature is verified.

US Patent:

8104029, Jan 24, 2012

Filed:

Apr 15, 2008

Appl. No.:

12/103705

Inventors:

Dibyendu Das - Bangalore, IN
Manish Gupta - Yorktown Heights NY, US
Rajan Ravindran - Bangalore, IN
Bhaskaran Venkatsubramaniam - Bangalore, IN

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 15/16
G06F 3/00
G06F 9/44
G06F 9/46
G06F 13/00

US Classification:

717151, 709205, 719313

Abstract:

A computer implemented method is provided for optimizing at the time of compiling a program that employs a message-passing interface (MPI). The method includes: detecting an MPI application source file; identifying a non-blocking communication within the MPI application source file; and overlapping independent computation concurrently with the non-blocking communication. A system is also provided.

US Patent:

8200945, Jun 12, 2012

Filed:

Nov 7, 2003

Appl. No.:

10/704214

Inventors:

Siddhartha Chatterjee - Yorktown Heights NY, US
Kenneth Dockser - Cary NC, US
Fred Gehrung Gustayson - Briarcliff Manor NY, US
Manish Gupta - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30

US Classification:

712218

Abstract:

A microprocessor includes a branch unit, a load/store unit (LSU), an arithmetic logic unit (ALU), and a vector unit to execute a vector instruction. The vector unit includes a vector register file having a primary vector register and a secondary vector register. The processor preferably further includes a first data bus and a second data bus wherein the first and second data busses couple the vector unit to the data memory. The vector unit includes a first input multiplexer enabling data on the first data bus to be provided to the primary register file or the secondary register file and a second input multiplexer, independent of the first input multiplexer enabling data on the second data bus to be provided to the second data bus. The first and second data busses may comprise first and second portions of a data memory bus.