Manouchehr R Entezari

US Patent:

8126401, Feb 28, 2012

Filed:

Mar 27, 2009

Appl. No.:

12/412790

Inventors:

Robert Bogdan Staszewski - Garland TX, US
Khurram Waheed - Plano TX, US
Sudheer K. Vemulapalli - Allen TX, US
Manouchehr Entezari - Highland Village TX, US
Imran Bashir - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04B 1/00

US Classification:

455 42, 455108, 455110, 375376

Abstract:

An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.

US Patent:

20080192877, Aug 14, 2008

Filed:

Feb 11, 2008

Appl. No.:

12/029456

Inventors:

Oren E. Eliezer - Plano TX, US
Manouchehr Entezari - Highland Village TX, US
Robert B. Staszewski - Garland TX, US
Sumeer Bhatara - Bangalore, IN

International Classification:

H04L 7/00

US Classification:

375376

Abstract:

A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.

US Patent:

20100135368, Jun 3, 2010

Filed:

Dec 2, 2008

Appl. No.:

12/326781

Inventors:

Jaimin A. Mehta - Plano TX, US
Sameh S. Rezeq - Dallas TX, US
Manouchehr Entezari - Highland Village TX, US
Robert B. Staszewski - Garland TX, US

International Classification:

H04B 1/38
G06F 17/17
H04L 25/03

US Classification:

375219, 708313, 375297

Abstract:

A novel and useful apparatus for and method of upsampling/interpolating a discrete-time input sample stream with time alignment utilizing the addition of randomized high frequency noise. The upsampling mechanism is an effective implementation of a second order interpolator that eliminates the need for a conventional filter as the filtering action is effectively built into the mechanism. The upsampling mechanism takes the derivative of the discrete-time input sample stream, thereby effectively providing another order of interpolation over a conventional interpolator. Before outputting the interpolated signal, an integrator takes the integral of the interpolated samples. Any processing performed between the derivative and integrator blocks effectively provides an additional order of interpolation. High frequency noise (i.e. dithering) is added to the differentiated samples in order to eliminate the spectral regrowth spurs that would otherwise appear in the output after rounding. Delay alignment is performed on the differentiated samples in order to time align both phase/frequency and amplitude samples that are processed on different paths.

US Patent:

20100188148, Jul 29, 2010

Filed:

Jan 26, 2009

Appl. No.:

12/359613

Inventors:

Jaimin A. Mehta - Plano TX, US
Sameh S. Rezeq - Dallas TX, US
Manouchehr Entezari - Highland Village TX, US
Robert B. Staszewski - Garland TX, US

International Classification:

H03F 1/26

US Classification:

330149

Abstract:

A novel and useful apparatus for and method of predistortion compensation of device (e.g., transistor) mismatch in a digital power amplifier (DPA). The device mismatch predistortion mechanism of the present invention addresses the problem of matching between two types of binary weighted transistors, whereby mismatched transistors cause degradation in wideband noise. The invention provides a digital predistortion mechanism which functions to pre-distort the mismatch ratio based on a data table calculated a priori enabling a polar transmitter to meet output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as GSM, 3G WCDMA, etc.

US Patent:

20120244824, Sep 27, 2012

Filed:

Aug 1, 2007

Appl. No.:

11/832292

Inventors:

Manouchehr Entezari - Highland Village TX, US
Robert B. Staszewski - Garland TX, US
Thomas Almholt - Murphy TX, US
Oren E. Eliezer - Plano TX, US

International Classification:

H04B 15/00
H04B 1/04

US Classification:

4551142

Abstract:

A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal. In direct coupling, the dither signal is coupled to the reference frequency input using a network of components directly connected thereto.

US Patent:

58869948, Mar 23, 1999

Filed:

Jul 1, 1996

Appl. No.:

8/673012

Inventors:

Stephen A. Deschaine - Garland TX
Manouchehr Entezari - Flower Mound TX
Mark J. Nietubyc - Plano TX
Werner L. Heissenhuber - Carrollton TX

Assignee:

Alcatel USA Sourcing, L.P. - Plano TX

International Classification:

H04J 302

US Classification:

370467

Abstract:

Apparatus and method are provided which map E1 signals into a logical space of a predetermined number of DS1 signals. 24 selected DS0 signals that are part of each E1 signal are mapped into the space of one DS1 signal in the logical space. The remaining eight DS0 signals of every three E1 signal are then interleavingly mapped into the space of one DS1 signal in the logical space. Depending on the defined logical space, additional E1 signals are mapped into the logical space in the same manner until the predetermined number of DS1 signal spaces in the defined logical space are filled.

US Patent:

59264802, Jul 20, 1999

Filed:

Jul 1, 1996

Appl. No.:

8/673118

Inventors:

Stephen A. Deschaine - Garland TX
Clemente G. Garcia - Garland TX
Edward P. Traupman - Fairview TX
Manouchehr Entezari - Flower Mound TX
Mark J. Nietubyc - Plano TX
Werner L. Heissenhuber - Carrollton TX

Assignee:

Alcatel USA Sourcing, L.P. - Plano TX

International Classification:

H04J 302

US Classification:

370401

Abstract:

An interface unit (12) for interfacing a digital loop carrier (16) to a digital cross-connect (14) comprises a control interface (22) coupled between the digital cross-connect (14) and digital loop carrier (16) for conversion and communication of control messages therebetween. A timing interface (32) is further coupled between the digital cross-connect (14) and digital loop carrier (16) for generally synchronizing the operations thereof. Further, a matrix interface (30) is coupled between the digital cross-connect (14) and digital loop carrier (16) for converting data rates and formats of data in the digital cross-connect (14) and digital loop carrier (16), so that network signals received by the digital loop carrier (16) are converted from a first format to a second format and communicated by the matrix interface (30) to the digital cross-connect (14) for cross-connection, and cross-connected data are converted from the second format to the first format and communicated to the digital loop carrier (16).

US Patent:

58751912, Feb 23, 1999

Filed:

Dec 17, 1996

Appl. No.:

8/768316

Inventors:

Stephen A. Deschaine - Garland TX
Manouchehr Entezari - Flower Mound TX
Rudolph B. Klecka - Dallas TX

Assignee:

DSC Telecom L.P. - Plano TX

International Classification:

H04J 302

US Classification:

370466

Abstract:

Two T1 signals are mapped onto a subscriber bus (26) in a subscriber loop equipment (10) for transport between a bank control unit (20) and channel units (22), for example. The data channels and the signaling and control channels of the first T1 signal are mapped onto a first data stream, and the data channels and the signaling and control channels of the second T1 signal are mapped onto a second data stream. The data streams are bit-interleaved for transport on the subscriber bus (26).