Marc C French

US Patent:

20200066515, Feb 27, 2020

Filed:

Jul 2, 2016

Appl. No.:

16/303125

Inventors:

- Santa Clara CA, US
Benjamin CHU-KUNG - Portland OR, US
Willy RACHMADY - Beaverton OR, US
Marc C. FRENCH - Forest Grove OR, US
Seung Hoon SUNG - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US
Matthew V. METZ - Portland OR, US
Ashish AGRAWAL - Hillsboro OR, US

International Classification:

H01L 21/02
H01L 29/10
H01L 29/66
H01L 29/78

Abstract:

An apparatus including a transistor device including a channel including germanium disposed on a substrate; a buffer layer disposed on the substrate between the channel and the substrate, wherein the buffer layer includes silicon germanium; and a seed layer disposed on the substrate between the buffer layer and the substrate, wherein the seed layer includes germanium. A method including forming seed layer on a silicon substrate, wherein the seed layer includes germanium; forming a buffer layer on the seed layer, wherein the buffer layer includes silicon germanium; and forming a transistor device including a channel on the buffer layer.

US Patent:

20190058043, Feb 21, 2019

Filed:

Mar 30, 2016

Appl. No.:

16/080101

Inventors:

- Santa Clara CA, US
Rafael Rios - Austin TX, US
Shriram Shivaraman - Hillsboro OR, US
Marko Radosavljevic - Portland OR, US
Kent E. Millard - Hillsboro OR, US
Marc C. French - Forest Grove OR, US
Van H. Le - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/40
H01L 29/221
H01L 29/423
H01L 29/417
H01L 29/66
H01L 29/78

Abstract:

Disclosed herein are transistor gate-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor gate-channel arrangement may include a channel material and a transistor gate stack. The transistor gate stack may include a gate electrode material, a high-k dielectric disposed between the gate electrode material and the channel material, and indium gallium zinc oxide (IGZO) disposed between the high-k dielectric material and the channel material.

US Patent:

20180366587, Dec 20, 2018

Filed:

Dec 23, 2015

Appl. No.:

15/777117

Inventors:

- Santa Clara CA, US
Gilbert DEWEY - Hillsboro OR, US
Rafael RIOS - Austin TX, US
Jack T. KAVALIEROS - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
Kent E. MILLARD - Hillsboro OR, US
Marc C. FRENCH - Forest Grove OR, US
Ashish AGRAWAL - Hillsboro OR, US
Benjamin CHU-KUNG - Hillsboro OR, US
Ryan E. ARCH - Hillsboro OR, US

International Classification:

H01L 29/786
H01L 29/06
H01L 29/24
H01L 29/423
H01L 29/49
H01L 21/02
H01L 29/40
H01L 29/66

Abstract:

Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

US Patent:

20180158933, Jun 7, 2018

Filed:

Jun 27, 2015

Appl. No.:

15/576468

Inventors:

- Santa Clara CA, US
Gilbert DEWEY - Hillsboro OR, US
Benjamin CHU-KUNG - Portland OR, US
Ashish AGRAWAL - Hillsboro OR, US
Matthew V. METZ - Portland OR, US
Willy RACHMADY - Beaverton OR, US
Marc C. FRENCH - Forest Grove OR, US
Jack T. KAVALIEROS - Portland OR, US
Rafael RIOS - Austin TX, US
Seiyon KIM - Portland OR, US
Seung Hoon SUNG - Portland OR, US
Sanaz K. GARDNER - Portland OR, US
James M. POWERS - Beaverton OR, US
Sherry R. TAFT - Sherwood OR, US

International Classification:

H01L 29/66
H01L 29/786

Abstract:

A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

US Patent:

20170317187, Nov 2, 2017

Filed:

Dec 23, 2014

Appl. No.:

15/528793

Inventors:

- Santa Clara CA, US
Willy RACHMADY - Beaverton OR, US
Matthew V. METZ - Portland OR, US
Gilbert DEWEY - Hillsboro OR, US
Jack T. KAVALIEROS - Portland OR, US
Chandra S. MOHAPATRA - Beaverton OR, US
Anand S. MURTHY - Portland OR, US
Nadia RAHHAL-ORABI - Hillsboro OR, US
Nancy M. ZELICK - Portland OR, US
Marc C. FRENCH - Forest Grove OR, US
Tahir GHANI - Portland OR, US

International Classification:

H01L 29/66
H01L 29/786
H01L 29/66
H01L 29/423
H01L 29/06
H01L 27/088
H01L 21/8234
H01L 21/02
H01L 21/02
H01L 29/786
H01L 21/02

Abstract:

An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

US Patent:

20170288019, Oct 5, 2017

Filed:

Jun 16, 2017

Appl. No.:

15/626018

Inventors:

- Santa Clara CA, US
Van H. LE - Portland OR, US
Ravi PILLARISETTY - Portland OR, US
Jessica S. KACHIAN - Portland OR, US
Marc C. FRENCH - Forest Grove OR, US
Aaron A. BUDREVICH - Portland OR, US

International Classification:

H01L 29/06

Abstract:

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

US Patent:

20170047401, Feb 16, 2017

Filed:

Oct 25, 2016

Appl. No.:

15/334112

Inventors:

- Santa Clara CA, US
Van H. LE - Portland OR, US
Ravi PILLARISETTY - Portland OR, US
Jessica S. KACHIAN - Portland OR, US
Marc C. FRENCH - Forest Grove OR, US
Aaron A. BUDREVICH - Portland OR, US

International Classification:

H01L 29/06
H01L 29/423
H01L 29/786
H01L 29/167
H01L 29/66
H01L 29/165
H01L 29/51

Abstract:

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

US Patent:

20160049476, Feb 18, 2016

Filed:

Oct 13, 2015

Appl. No.:

14/756789

Inventors:

- Santa Clara CA, US
Van H. Le - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Jessica S. Kachian - Portland OR, US
Marc C. French - Forest Grove OR, US
Aaron A. Budrevich - Portland OR, US

International Classification:

H01L 29/167
H01L 29/78
H01L 29/161

Abstract:

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.