Marc P Robinson

US Patent:

7215018, May 8, 2007

Filed:

Mar 25, 2005

Appl. No.:

11/090969

Inventors:

Al Vindasius - Saratoga CA, US
Marc Robinson - San Jose CA, US
Larry Jacobsen - Bend OR, US
Donald Almen - San Martin CA, US

Assignee:

Vertical Circuits, Inc. - Scotts Valley CA

International Classification:

H01L 23/02

US Classification:

257686, 257777

Abstract:

The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

US Patent:

7245021, Jul 17, 2007

Filed:

Mar 31, 2005

Appl. No.:

11/097829

Inventors:

Al Vindasius - Saratoga CA, US
Marc Robinson - San Jose CA, US
Larry Jacobsen - Bend OR, US
Donald Almen - San Martin CA, US

Assignee:

Vertical Circuits, Inc. - Scotts Valley CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257777, 257686

Abstract:

The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

US Patent:

7535109, May 19, 2009

Filed:

May 3, 2007

Appl. No.:

11/744153

Inventors:

Marc E. Robinson - San Jose CA, US
Alfons Vindasius - Saratoga CA, US
Donald Almen - San Martin CA, US
Larry Jacobsen - Bend OR, US

Assignee:

Vertical Circuits, Inc. - Scotts Valley CA

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257777, 257686

Abstract:

The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

US Patent:

7705432, Apr 27, 2010

Filed:

Dec 17, 2004

Appl. No.:

11/016558

Inventors:

Al Vindasius - Saratoga CA, US
Marc Robinson - San Jose CA, US

Assignee:

Vertical Circuits, Inc. - Scotts Valley CA

International Classification:

H01L 23/58

US Classification:

257642, 257594, 257622, 257E23002

Abstract:

Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

US Patent:

8178978, May 15, 2012

Filed:

Mar 12, 2009

Appl. No.:

12/403175

Inventors:

Simon J. S. McElrea - Scotts Valley CA, US
Marc E. Robinson - San Jose CA, US

Assignee:

Vertical Circuits, Inc. - Scotts Valley CA

International Classification:

H01L 23/495
H01L 23/50
H01L 23/34
H01L 25/16
H01L 21/50

US Classification:

257777, 257773, 257E21599, 257E2301, 257735, 257E23014, 257E23001, 257686, 257E25013, 257E23146, 257676, 257712, 257713, 257E21499, 257E23031, 257E2308, 257E25029, 257737, 257738, 257778, 257691, 257696, 257698

Abstract:

Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to any interposed substrate or leadframe, and without solder.

US Patent:

8357999, Jan 22, 2013

Filed:

May 3, 2007

Appl. No.:

11/744142

Inventors:

Marc E. Robinson - San Jose CA, US
Alfons Vindasius - Saratoga CA, US
Donald Almen - San Martin CA, US
Larry Jacobsen - Bend OR, US

Assignee:

Vertical Circuits (Assignment for the Benefit of Creditors), LLC - Mountain View CA

International Classification:

H01L 23/522

US Classification:

257686, 257777, 257E23085

Abstract:

The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by attaching a short flexible bond wire or bond ribbon to the exposed electrical connection pad at the peripheral edges of the die which protrudes horizontally from the die and applying electrically conductive polymer, or epoxy, filaments or lines to one or more sides of the stack.

US Patent:

8629543, Jan 14, 2014

Filed:

Oct 27, 2010

Appl. No.:

12/913604

Inventors:

Simon J. S. McElrea - Scotts Valley CA, US
Scott McGrath - Scotts Valley CA, US
Terrence Caskey - Santa Cruz CA, US
Scott Jay Crane - Aromas CA, US
Marc E. Robinson - San Jose CA, US
Loreto Cantillep - San Jose CA, US

Assignee:

Invensas Corporation - San Jose CA

International Classification:

H01L 23/02

US Classification:

257686

Abstract:

In die stack assembly configurations successive die in the stack are offset at a die edge at which die pads are situated, and the die are interconnected by electrically conductive traces. In some embodiments the electrically conductive traces are formed of an electrically conductive polymer. An electrically insulative conformal coating is provided having openings at die pads that are electrically connected.

US Patent:

20070290377, Dec 20, 2007

Filed:

Aug 31, 2007

Appl. No.:

11/849162

Inventors:

Al Vindasius - Saratoga CA, US
Marc Robinson - San Jose CA, US

Assignee:

Vertical Circuits, Inc. - Scotts Valley CA

International Classification:

H01L 23/29
H01L 21/56

US Classification:

257788000, 438127000, 257E23117, 257E21502

Abstract:

Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.