Marcio A Oliveira

US Patent:

7756148, Jul 13, 2010

Filed:

Jun 8, 2007

Appl. No.:

11/760699

Inventors:

Marcio T. Oliveira - San Jose CA, US
Robert A. Alfieri - Chapel Hill NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

370412, 370428, 710 52

Abstract:

Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.

US Patent:

8201172, Jun 12, 2012

Filed:

Jun 8, 2007

Appl. No.:

11/760697

Inventors:

Marcio T. Oliveira - San Jose CA, US
Robert A. Alfieri - Chapel Hill NC, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

Systems and methods storing data for multi-threaded processing permit multiple execution threads to store data in a single first-in first-out (FIFO) memory. Threads are assigned to classes, with each class including one or more threads. Each class may be allocated dedicated entries in the FIFO memory. A class may also be allocated shared entries in the FIFO memory. The shared entries may be used by any thread. Data for a first thread may be stored in the FIFO memory while data for a second thread is read from the FIFO memory, even when the first thread and the second thread are not in the same class. The FIFO memory may include a speculative read and a speculative write capability. The FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory.

US Patent:

8429661, Apr 23, 2013

Filed:

Dec 14, 2005

Appl. No.:

11/304959

Inventors:

Robert A. Alfieri - Chapel Hill NC, US
Marcio T. Oliveira - San Jose CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 9/46
G06F 13/00

US Classification:

718104, 711147

Abstract:

Systems and methods storing data for multi-threaded processing permit multiple execution threads to store data in a single first-in first-out (FIFO) memory. Threads are assigned to classes, with each class including one or more threads. Each class may be allocated dedicated entries in the FIFO memory. A class may also be allocated shared entries in the FIFO memory. The shared entries may be used by any thread. Data for a first thread may be stored in the FIFO memory while data for a second thread is read from the FIFO memory, even when the first thread and the second thread are not in the same class. The FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory.

US Patent:

7630389, Dec 8, 2009

Filed:

Apr 6, 2006

Appl. No.:

11/399247

Inventors:

Robert A. Alfieri - Chapel Hill NC, US
Marcio T. Oliveira - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

370412, 370428, 710 52

Abstract:

Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.