Marcus T Baker

US Patent:

7523365, Apr 21, 2009

Filed:

Dec 19, 2005

Appl. No.:

11/305932

Inventors:

Alfredo Aldereguia - Cary NC, US
Marcus Alan Baker - Apex NC, US
Justin Potok Bandholz - Cary NC, US
Jeffrey Buchanan Williams - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 31/28
G06F 11/00
G11B 27/00
H04B 3/46

US Classification:

714712, 714798, 714819, 375224

Abstract:

A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (V) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.

US Patent:

7562247, Jul 14, 2009

Filed:

May 16, 2006

Appl. No.:

11/434611

Inventors:

Marcus A. Baker - Apex NC, US
Justin P. Bandholz - Cary NC, US
Patrick M. Bland - Raleigh NC, US
Andrew S. Heinzmann - Apex NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00
G06F 11/20

US Classification:

714 2, 714 3, 713501, 713503

Abstract:

Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.

US Patent:

8180862, May 15, 2012

Filed:

Aug 30, 2007

Appl. No.:

11/847568

Inventors:

Marcus A. Baker - Apex NC, US
Marlene J. Gillingham - Bellevue WA, US
Mark V. Kapoor - Durham NC, US
Sheldon J. Sigrist - Cary NC, US
Karen A. Taylor - Cary NC, US
Steven J. Zaharias - Issaquah WA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/177

US Classification:

709220, 709201, 709202, 709221, 709222

Abstract:

In some embodiments, a method for auto-configuring a network is disclosed. The method can include communicating with at least one node in a processing complex, receiving node connection data from the at least one node querying a node to verify at least a portion of the node connection data, and auto-configuring system partitioning in response to the node connection data. In some embodiments, the method can also include verifying the node connection data by transmitting a request for a universally unique identifier and a node identifier. The node identifier can be associated with the universally unique identifier. The node identifier can be utilized in data transmitted between nodes.

US Patent:

20040264285, Dec 30, 2004

Filed:

Jun 30, 2003

Appl. No.:

10/609892

Inventors:

Marcus Baker - Apex NC, US
Jeffrey Williams - Raleigh NC, US
Sheldon Sigrist - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C008/02

US Classification:

365/232000

Abstract:

Method and system for saving the state of integrated circuit chips upon failure. In one aspect of the invention, a system for saving the state of an integrated circuit includes a non-volatile memory and a state-saving controller coupled to the non-volatile memory and coupled to the integrated circuit, where the state-saving controller saves the state of the integrated circuit to the non-volatile memory when a failure occurs in the integrated circuit.

US Patent:

20080140895, Jun 12, 2008

Filed:

Dec 9, 2006

Appl. No.:

11/608817

Inventors:

Marcus A. Baker - Apex NC, US
Cody I. Gillians - Raleigh NC, US
Mauricio Gonzalez - Cary NC, US
Randolph S. Kolvick - Durham NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 13/24

US Classification:

710262

Abstract:

Methods and arrangements for managing interrupts in a processing system are disclosed. The method can determine an indication of an interrupt request from a peripheral entity, identify the peripheral entity associated with the indication, count occurrences of the indications; and flag the peripheral entity in response to the counted occurrences. When the counted occurrences reach a predetermined number in the predetermined time interval, interrupts from the peripheral entity can be ignored or the entity can be identified as having possible operational problems.

US Patent:

20080288828, Nov 20, 2008

Filed:

Jul 30, 2008

Appl. No.:

12/182553

Inventors:

Marcus A. Baker - Apex NC, US
Cody I. Gillians - Raleigh NC, US
Mauricio Gonzalez - Cary NC, US
Randolph S. Kolvick - Durham NC, US

International Classification:

G06F 11/30

US Classification:

714 47, 714E11179

Abstract:

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for managing interrupts in a processing system are disclosed. The design structure can determine an indication of an interrupt request from a peripheral entity, identify the peripheral entity associated with the indication, count occurrences of the indications; and flag the peripheral entity in response to the counted occurrences. When the counted occurrences reach a predetermined number in the predetermined time interval, interrupts from the peripheral entity can be ignored or the entity can be identified as having possible operational problems.