Maria Christina Mar

US Patent:

6425111, Jul 23, 2002

Filed:

Dec 30, 1999

Appl. No.:

09/475733

Inventors:

Maria del Mar Hershenson - Palo Alto CA

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 4, 702 58, 702109, 702118, 703 2, 703 14

Abstract:

A method for providing a mathematical expression representing the operation of a field-effect transistor in its saturation region is disclosed. Data representing the operation of the transistor is divided into data segments with a monomial function fitted to each of the segments. The data segments are selected for a particular operating parameter such as transconductance based on knowledge of the transistor operation. The error at the transition from one function to another is checked and the data segments redivided to minimize the error. The resulting expression lends itself to global solution with geometric programs.

US Patent:

6954921, Oct 11, 2005

Filed:

Apr 7, 2002

Appl. No.:

10/118672

Inventors:

Arash Hassibi - Mountain View CA, US
Maria del Mar Hershenson - Los Altos CA, US
David M. Colleran - San Mateo CA, US

Assignee:

Barcelona Design, Inc. - Newark CA

International Classification:

G06F017/50

US Classification:

716 18, 716 2

Abstract:

A method is described that involves recognizing that a variable within a monomial or posynomial expression for a characteristic of an analog or mixed signal system has a dependency on a lower level expression. Then, retrieving from a database the lower level expression and substituting it into the expression in place of the variable so as to describe the system at a greater level of detail than the variable did.

US Patent:

7093205, Aug 15, 2006

Filed:

Apr 10, 2003

Appl. No.:

10/412535

Inventors:

Thomas Heydler - Danville CA, US
Maria del Mar Hershenson - Palo Alto CA, US

Assignee:

Barcelona Design, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 3, 716 5

Abstract:

A method is described that involves automatically generating a physical behavior curve from a process description; where, the process description describes a process. The method also involves automatically generating a device model for the process from the physical behavior curve; where, the device model is represented in geometric form. The method also involves attempting to automatically generate, with the device model and with a geometric optimization sequence, a circuit design for the process.

US Patent:

8307309, Nov 6, 2012

Filed:

Aug 20, 2008

Appl. No.:

12/195326

Inventors:

Maria del Mar Hershenson - Los Altos CA, US
Sunderarajan S. Mohan - Mountain View CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 51, 716111, 716136

Abstract:

A method is described that involves identifying a subset of operational scenarios for a circuit being designed. The family of equations are solved for the circuit over the subset and the solving produces numeric values for design parameters of the circuit. The family of equations enhanced with said numeric values are solved over a remainder of the scenarios and none of the remaining scenarios are identified as being infeasible scenarios. A design for the circuit that includes the numeric values is produced.

US Patent:

8635564, Jan 21, 2014

Filed:

Mar 25, 2013

Appl. No.:

13/850280

Inventors:

Maria Del Mar Hershenson - Los Altos CA, US
David M. Colleran - Los Altos CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716100, 716132, 716135

Abstract:

Methods for optimizing design parameters of a circuit are disclosed. In one aspect, an optimization problem includes one or more performance specifications that represent an exponent of a design parameter to be optimized. Various parameters of passive and active circuit devices may be efficiently and accurately optimized as a result. In another aspect, linear performance specifications are included for accurately calculating voltages. In yet other aspects of the invention, three special types of convex optimization problems are disclosed for enabling the above use of exponents of design parameters which provide efficient and accurate calculations of a virtually unlimited array of circuit parameters and performance characteristics.

US Patent:

20130125081, May 16, 2013

Filed:

Nov 5, 2012

Appl. No.:

13/669342

Inventors:

Maria del Mar Hershenson - Los Altos CA, US
Sunderarajan S. Mohan - Mountain View CA, US

International Classification:

G06F 17/50

US Classification:

716133

Abstract:

A method is described that involves solving a family of equations for a circuit being designed over a subset of operational scenarios, thereby producing numeric values for design parameters of the circuit. The family of equations is enhanced with the numeric values are solved over a second subset of the operational scenarios. A design for the circuit that includes the numeric values is produced.

US Patent:

62692771, Jul 31, 2001

Filed:

Jul 27, 1998

Appl. No.:

9/123129

Inventors:

Maria del Mar Hershenson - Palo Alto CA
Stephen P. Boyd - Stanford CA
Thomas H. Lee - Cupertino CA

Assignee:

The Leland Stanford Junior University Board of Trustees - Palo Alto CA

International Classification:

G06F 1900

US Classification:

700 97

Abstract:

A system for designing and optimizing integrated circuits. Design objectives and constraints are described as posynomial functions of the design parameters. The circuit design problem is then expressed as a special form of optimization problem called geometric programming, to which very efficient global optimization methods are applied. The present invention can thereby efficiently determine globally optimal circuit designs, or globally optimal trade-offs among competing performance measures such as, for example for an operational amplifier (op-amp), power, open-loop gain, and bandwidth. The present invention therefore yields automated synthesis of globally optimal circuit designs for a given circuit topology library, directly from specifications.

US Patent:

63111454, Oct 30, 2001

Filed:

Jun 17, 1999

Appl. No.:

9/335227

Inventors:

Maria del Mar Hershenson - Palo Alto CA
Stephen P. Boyd - Stanford CA
Sunderarajan S. Mohan - Mountain View CA

Assignee:

The Board of Trustees of the LeLand Stanford Junior University - Palo Alto CA

International Classification:

G06F 1750
G06F 1711

US Classification:

703 2

Abstract:

A method for the design and optimization of inductors for RF circuits. This method consists in the formulation of RF circuit designs as geometric programs. The designer can specify a wide variety of specifications such as gain, bandwidth, noise, etc. The method, which was implemented in simple code, determines inductor dimensions and component values in a few seconds real-time. The results was also a globally optimal design.