Marielle C Bundukin

US Patent:

20120320679, Dec 20, 2012

Filed:

May 17, 2012

Appl. No.:

13/474055

Inventors:

Steven T. Sprouse - San Jose CA, US
Sergey Anatolievich Gorobets - Edinburgh, GB
William Wu - Cupertino CA, US
Alan Bennett - Edinburgh, GB
Marielle Bundukin - Hayward CA, US

International Classification:

G11C 16/04

US Classification:

36518512

Abstract:

A system and method for reducing write amplification while maintaining a desired level of sequential read and write performance is disclosed. A controller in a multi-bank flash storage device may receive host data for writing to the plurality of flash memory banks. The controller may organize the received data in multi-page logical groups greater than a physical page and less than a physical block and interleave writes of the host data to the memory banks with that striping factor. A buffer RAM is associated with each bank of the multi-bank memory where the buffer RAM is sized as equal to or greater than the size of the multi-page logical group.

US Patent:

20130073784, Mar 21, 2013

Filed:

Sep 15, 2011

Appl. No.:

13/233540

Inventors:

King Ying Ng - San Jose CA, US
Marielle Bundukin - Hayward CA, US
Paul Lassa - Cupertino CA, US

International Classification:

G06F 12/00

US Classification:

711103, 711154, 711104, 711E12001

Abstract:

A method and system are disclosed for handling host write commands associated with both data aligned with physical page boundaries of parallel write increments in non-volatile storage areas in a non-volatile storage device and data unaligned with the physical page boundaries. The method may include a controller of a storage device identifying the aligned and unaligned portions of received data, temporarily storing the aligned and unaligned portions in different queues, and then writing portions from the unaligned data queue or the aligned data queue in parallel to the non-volatile memory areas when one of the queues has been filled with a threshold amount of data or when the controller detects a timeout condition. The system may include a storage device with a controller configured to perform the method noted above, where the non-volatile memory areas may be separate banks and the queues are random access memory.

US Patent:

20130173842, Jul 4, 2013

Filed:

Dec 28, 2011

Appl. No.:

13/338941

Inventors:

King Ying Ng - Fremont CA, US
Marielle Bundukin - Hayward CA, US
Paul A. Lassa - Cupertino CA, US
Sergey A. Gorobets - Edinburgh, GB
Liam Parker - Edinburgh, GB

International Classification:

G06F 12/00

US Classification:

711103, 711E12008

Abstract:

A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory and determining if a threshold amount of data has been received. When the threshold amount of data is received, the non-volatile memory is scanned for sequentially numbered logical groups of data previously written in noncontiguous locations in the non-volatile memory. When a threshold amount of such sequentially numbered logical groups is found, the controller re-writes the sequentially numbered logical groups of data contiguously into a new block. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data into new blocks may be fixed or variable.

US Patent:

20120297122, Nov 22, 2012

Filed:

May 10, 2012

Appl. No.:

13/468737

Inventors:

Sergey Anatolievich Gorobets - Edinburgh, GB
Alan David Bennett - Edinburgh, GB
Tom Hugh Shippey - Edinburgh, GB
Liam Michael Parker - Edinburgh, GB
Yauheni Yaromenka - Gomel, BY
Steven T. Sprouse - San Jose CA, US
William S. Wu - Cupertino CA, US
Marielle Bundukin - Hayward CA, US

International Classification:

G06F 12/02

US Classification:

711103, 711E12008, 711E12009

Abstract:

A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.

US Patent:

20140281132, Sep 18, 2014

Filed:

Mar 15, 2013

Appl. No.:

13/838582

Inventors:

Marielle Bundukin - Hayward CA, US
King Ying Ng - Fremont CA, US
Steven T. Sprouse - San Jose CA, US
William Wu - Cupertino CA, US
Sergey Anatolievich Gorobets - Edinburgh, GB
Liam Parker - Edinburgh, GB
Alan David Bennett - Edinburgh, GB

International Classification:

G06F 12/02

US Classification:

711103

Abstract:

A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above.