Mark Aaron Alexander

US Patent:

6961231, Nov 1, 2005

Filed:

Mar 8, 2005

Appl. No.:

11/074967

Inventors:

Mark A. Alexander - San Francisco CA, US
Robert O. Conn - Los Gatos CA, US
Steven J. Carey - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01G004/06

US Classification:

3613212, 3613011, 3613061, 361311, 361313, 361320, 361736, 361766, 257738, 257744, 257777, 257780, 174250, 174256, 174262

Abstract:

Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

US Patent:

7511299, Mar 31, 2009

Filed:

Oct 2, 2007

Appl. No.:

11/906669

Inventors:

Mark A. Alexander - San Francisco CA, US
Paul Ying-Fung Wu - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 23/58

US Classification:

257 48

Abstract:

A packaged integrated circuit (“IC”) includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.

US Patent:

7949979, May 24, 2011

Filed:

Aug 13, 2008

Appl. No.:

12/190729

Inventors:

Mark A. Alexander - San Francisco CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716115, 716106, 716111, 716136

Abstract:

Induced crosstalk is predicted for the input/output pins of a programmable logic device. Signal edge rates for the input/output pin are determined from selected interface protocols for the input/output pins. For each pair of the input/output pins, a first coupling coefficient specifies a coupling between the pair of input/output pins within a package for mounting the programmable logic device to a printed circuit board. A depth is input for each via coupled to an input/output pin by the printed circuit board. From the via depths, a second coupling coefficient is determined for each pair of the input/output pins that satisfy a separation criterion. For each of the input/output pins, a predicted value of an induced crosstalk is determined from the first and second coupling coefficients for each pair that includes the input/output pin and another input/output pin, and from the signal edge rate of this other input/output pin.

US Patent:

8086435, Dec 27, 2011

Filed:

Dec 11, 2008

Appl. No.:

12/333151

Inventors:

Mark A. Alexander - San Francisco CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 716113, 716115

Abstract:

A method for the prediction of simultaneous switching output (SSO) noise that may be generated by one or more signal conduction paths within an electrical system. Electrical disturbance waveforms are first recorded for each signal conduction path that may be affected by the electrical disturbances. Next, principles of superposition are utilized to coherently combine each of the electrical disturbance waveforms in the time domain to generate the predicted SSO noise waveform that is imposed upon the affected signal conduction path. The electrical disturbance waveforms may be produced either by using bench measurements performed on an actual integrated circuit, by simulation, or by a combination of simulation and bench measurements.

US Patent:

8258845, Sep 4, 2012

Filed:

May 20, 2005

Appl. No.:

11/134117

Inventors:

Mark A. Alexander - San Francisco CA, US
Sean A. Koontz - Hollister CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 3/00

US Classification:

327291

Abstract:

The relative timing of triggering switching events in a circuit block of an IC device is dynamically adjusted in response to fluctuations in device's supply voltage to minimize clock jitter caused by supply voltage noise. A control circuit monitors supply voltage fluctuations, and in response thereto dynamically phase-shifts a clock signal that triggers the switching events so that the switching events occur during relatively quiet time intervals in which fluctuations in the supply voltage are minimal.

US Patent:

8412497, Apr 2, 2013

Filed:

Sep 7, 2010

Appl. No.:

12/876967

Inventors:

Mark A. Alexander - San Francisco CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 2, 703 14, 716104, 716115, 716136

Abstract:

Predicting simultaneous switching output noise of an IC device is described. User input is obtained. The user input includes: an identification of an input/output bank of an integrated circuit die; an identification of a device package substrate to which the integrated circuit die is to be attached; and an identification of input/output interface to be used by the input/output bank. A noise factor and an impedance are selected responsive to the user input. The noise factor is multiplied with the impedance to provide a result. The result, which is output, is a prediction of the simultaneous switching output noise of the integrated circuit device.

US Patent:

8521485, Aug 27, 2013

Filed:

Jun 25, 2010

Appl. No.:

12/824110

Inventors:

Mark A. Alexander - San Francisco CA, US
Austin Tavares - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/445

US Classification:

703 2, 703 6, 703 14, 716104, 257499

Abstract:

Approaches for analyzing a power grid of an integrated circuit are described. In one embodiment, a method includes selecting at least one portion of the integrated circuit to be analyzed. A power grid model corresponding to the integrated circuit is retrieved from a database, and a first simulation of the programmable integrated circuit is performed. The first simulation generates a respective waveform of an electrical characteristic over time for each connection of a component within the selected portion to voltage supply or voltage ground. A simulation is performed of the power grid model using the respective waveforms as input stimulus for each connection in the selected portion.

US Patent:

43909817, Jun 28, 1983

Filed:

Dec 29, 1980

Appl. No.:

6/220375

Inventors:

Leonard J. Wood - San Mateo CA
Balakrishna Parasuraman - Sunnyvale CA
Edwin H. Williams - Sunnyvale CA
Mark G. Alexander - Mountain View CA
Richard C. Montgomery - Santa Clara CA

Assignee:

Syscom, Inc. - Sunnyvale CA

International Classification:

H04J 304

US Classification:

370 56

Abstract:

A message handling system includes a computer controlled message processor for use in network configurations to store and forward low-speed messages between long distance and international communicators. Its use is based on dial-up connections between network nodes. Each message handler unit includes a microprocessor, program and buffer storage memories, line multiplexing circuitry, modems and input/output peripheral devices. The message handler unit may comprise a 32 port system, 30 of which are used as input ports and two of which are used as high-speed output ports. A journal of all message numbers is maintained on a printer for complete message accountability.