Mark T Anders

US Patent:

6522186, Feb 18, 2003

Filed:

Jun 27, 2001

Appl. No.:

09/893067

Inventors:

Frank OMahony - San Carlos CA
Mark A. Anders - Hillsboro OR
Krishnamurthy Soumyanath - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 104

US Classification:

327295, 327293, 327297

Abstract:

A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.

US Patent:

6909127, Jun 21, 2005

Filed:

Jun 27, 2001

Appl. No.:

09/893023

Inventors:

Frank O'Mahony - San Carlos CA, US
Mark A. Anders - Hillsboro OR, US
Krishnamurthy Soumyanath - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L027/10

US Classification:

257208, 257776, 327295

Abstract:

A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e. g. , orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

US Patent:

6993942, Feb 7, 2006

Filed:

Nov 14, 2002

Appl. No.:

10/295020

Inventors:

Christopher Boni - Livingston NJ, US
Mark Anders - Providence RI, US

International Classification:

E05B 73/00

US Classification:

70 18, 70 14, 70 57

Abstract:

An adjustable locking strap apparatus for locking an elongate object includes a first loop, a second loop, and an adjustable strap extending therebetween. The loops can be fit about ends of the elongate object. One loop could be adjusted adjusted for proper size. The strap extending between the loops can be adjusted between the loops so that when the first and second loops are positioned about the elongate object, the strap is sized to prevent either loop from being removed from the object. A lock is interconnected with the adjustable loop and strap for securing the size of the adjustable loop and strap. A tether portion can secure the locking strap to a fixed object. A stopper on the tether can be positioned within a car, and the window rolled up to retain the locking strap within a car. In other embodiments, two straps with loops at one end and stoppers at the other end can used. One loop is positioned about an end of the elongate object and the strap is retained in a housing.

US Patent:

7352059, Apr 1, 2008

Filed:

Jun 14, 2005

Appl. No.:

11/152643

Inventors:

Frank O'Mahony - San Carlos CA, US
Mark A. Anders - Hillsboro OR, US
Krishnamurthy Soumyanath - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 27/10
H01L 23/52
H01L 23/522
H01R 12/00

US Classification:

257691, 257E23144, 257208, 257758, 257775, 257776, 257664, 257211, 257E23011, 439 65, 327295

Abstract:

A low loss on-die interconnect structure includes first and second differential signal lines on one of the metal layers of a microelectronic die. One or more traces may also be provided on another metal layer of the die that are non-parallel (e. g. , orthogonal) to the differential signal lines. Because the traces are non-parallel, they provide a relatively high impedance return path for signals on the differential signal lines. Thus, a signal return path through the opposite differential line predominates for the signals on the differential lines. In one application, the low loss interconnect structure is used within an on-die salphasic clock distribution network.

US Patent:

7707152, Apr 27, 2010

Filed:

Jul 29, 2005

Appl. No.:

11/192985

Inventors:

Eliot Greenfield - Oakland CA, US
Mark Anders - San Francisco CA, US
Sho Kuwamoto - San Francisco CA, US
Todd Rein - San Francisco CA, US

Assignee:

Adobe Systems Incorporated - San Jose CA

International Classification:

G06F 7/00
G06F 17/00

US Classification:

707100, 707 1, 707 3, 7071041

Abstract:

Systems and methods which facilitate search engine discovery of and/or access to application program content are shown. Declarative code may be provided within the procedural code of a rich Internet application in order to identify various states, and their associated content, of the rich Internet application. A Web crawler may identify content associated with a rich Internet application using the foregoing information. Likewise, direct access to rich Internet application states associated with the identified content may be provided using the foregoing information. A translation module may be provided for interfacing between a Web crawler and a rich Internet application. Such a translation module may interact with the Web crawler to respond to Web crawler navigation instructions and access declarative code associated with different states of the rich Internet application, providing responsive information identifying content in a structure that is compatible with a search engine associated with the Web crawler.

US Patent:

7945863, May 17, 2011

Filed:

Jul 5, 2005

Appl. No.:

11/175114

Inventors:

Dexter Reid - San Francisco CA, US
Narciso B. Jaramillo - San Francisco CA, US
Mark Anders - San Francisco CA, US

Assignee:

Adobe Systems Incorporated - San Jose CA

International Classification:

G06F 3/048
G06F 3/00
G09G 5/00

US Classification:

715797, 715762, 715763, 715767, 345651, 345660, 345665, 345671

Abstract:

A method for providing an Integrated Development Environment comprises receiving input from a user identifying an area containing an edge shared by two or more objects, wherein the shared edge includes two or more individual edges corresponding to the objects, and visibly separating the two or more individual edges in a localized exploded view responsive to the receiving.

US Patent:

7949991, May 24, 2011

Filed:

Jul 29, 2005

Appl. No.:

11/194118

Inventors:

Sho Kuwamoto - San Francisco CA, US
Eliot Greenfield - Oakland CA, US
Mark Anders - San Francisco CA, US

Assignee:

Adobe Systems Incorporated - San Jose CA

International Classification:

G06F 9/44

US Classification:

717100

Abstract:

Systems and methods which implement declarative language for specifying states within imperative code are shown. According to embodiments an application program developer declaratively identifies one or more states within the imperative code of the application program. Declarative language identifying a particular state of an application program may both operate to identify the state and to describe the state so that the state may be selected or “jumped to” without a user having to navigate the application program flow to arrive at the state. Particular states may be described using a difference or “delta” between the particular state and another state, such as a base state. Transitions may be implemented between states, such as to provide animation, fading, color change, et cetera.

US Patent:

8280884, Oct 2, 2012

Filed:

Mar 3, 2010

Appl. No.:

12/716390

Inventors:

Eliot Greenfield - Oakland CA, US
Mark Anders - San Francisco CA, US
Sho Kuwamoto - San Francisco CA, US
Todd Rein - San Francisco CA, US

Assignee:

Adobe Systems Incorporated - San Jose CA

International Classification:

G06F 7/00
G06F 17/30

US Classification:

707736, 707721, 707754, 707767

Abstract:

Systems and methods which facilitate search engine discovery of and/or access to application program content are shown. Declarative code may be provided within the procedural code of a rich Internet application in order to identify various states, and their associated content, of the rich Internet application. A Web crawler may identify content associated with a rich Internet application using the foregoing information. Likewise, direct access to rich Internet application states associated with the identified content may be provided using the foregoing information. A translation module may be provided for interfacing between a Web crawler and a rich Internet application. Such a translation module may interact with the Web crawler to respond to Web crawler navigation instructions and access declarative code associated with different states of the rich Internet application, providing responsive information identifying content in a structure that is compatible with a search engine associated with the Web crawler.