Mark Aladar Appel

US Patent:

20130234871, Sep 12, 2013

Filed:

Mar 6, 2013

Appl. No.:

13/787718

Inventors:

Ryan Lobo - Richardson TX, US
Mark Appel - Plano TX, US

Assignee:

XW, LLC d/b/a Xtendwave - Dallas TX

International Classification:

H03M 1/10

US Classification:

341120

Abstract:

Cost-effective structures and methods that allow an integrated digital-to-analog converter (DAC) to simultaneously achieve wide dynamic ranges and bandwidths through the use of built-in measurement and compensation mechanisms that are primarily digital. The measurements of the DAC's distortions are made with a relatively simple analog-to-digital converter (ADC) that is not designed to accommodate the combination of the bandwidth and the resolution offered by the DAC, but is nonetheless sufficient in determining the characteristics of the DAC's impairments during a calibration procedure. This information is then used in a feed-forward compensation system during the DAC's normal operation to estimate and cancel the distortions in its output signal that could result from the various impairments.

US Patent:

62230565, Apr 24, 2001

Filed:

Dec 31, 1997

Appl. No.:

9/001760

Inventors:

Mark J. Appel - Richardson TX

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

H04B 138
H04B 104
H04B 1700

US Classification:

455561

Abstract:

There is disclosed, for use in a wireless communication system comprising at least one base station operable to communicate with a plurality of mobile units, a power controller for controlling a power consumption of a linear power amplifier in the base station. The power controller comprises: 1) a first power monitor for determining an RF output power level of the linear power amplifier; 2) a second power monitor for determining a primary power level consumed by the linear power amplifier; and 3) a processing circuit operable to determine an actual power ratio of the primary power level and the RF output power level and to adjust the primary power level to maintain the actual power ratio at approximately a selected target power ratio.

US Patent:

62723367, Aug 7, 2001

Filed:

Dec 30, 1998

Appl. No.:

9/222899

Inventors:

Mark J. Appel - Richardson TX
Mitchell K. Johnson - McKinney TX

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

H04Q 720

US Classification:

455423

Abstract:

There is disclosed a power control circuit for controlling the combined effective DC bias current of a bank of parallel RF power amplifiers disposed in the transmit path of an RF transmitter. The power control circuit comprises: 1) a first signal monitor for monitoring the level of a modulated RF output signal; and 2) an amplifier bias current controller for comparing the modulated RF output signal level and a known maximum output power parameter of the active RF power amplifiers to determine if the active RF power amplifiers are operating in the linear region. If the active RF power amplifiers are operating in or near the nonlinear region, the power control circuit enables one or more inactive RF power amplifiers to increase the effective combined DC bias current and linearity of the active RF power amplifiers. Conversely, if the active RF power amplifiers are operating well within the linear region, the power control circuit may disable one or more active RF power amplifiers in order to reduce the effective combined DC bias current of the active RF power amplifiers and save power.

US Patent:

62153587, Apr 10, 2001

Filed:

Sep 16, 1999

Appl. No.:

9/397224

Inventors:

Terry Hon - Wylie TX
Mark J. Appel - Richardson TX
George A. Bednekoff - Plano TX

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

H03F 304

US Classification:

330289

Abstract:

There is disclosed, for use in an RF amplifier, a biasing circuit for maintaining the quiescent current of an output power transistor at a selected bias level. The biasing circuit comprises a temperature sensor circuit for generating a temperature-sensitive control voltage that varies according to changes in temperature of the output power transistor and a bias voltage generating circuit capable of detecting a variation in the temperature-sensitive control voltage. In response to a detected change in the temperature-sensitive control voltage, the bias circuit adjusts a bias voltage applied to the output power transistor by an amount suitable to offset a change in the selected bias current level caused by a temperature change related to the variation in the temperature-sensitive voltage.