Mark M Frank

US Patent:

6711730, Mar 23, 2004

Filed:

May 13, 2002

Appl. No.:

10/179077

Inventors:

Mark D. Frank - Longmont CO
William Bryson McHardy - Ft. Collins CO
Peter Shaw Moldauer - Wellington CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 18, 716 17, 716 6

Abstract:

Techniques are disclosed for automatically synthesizing information from a plurality of computer-readable integrated circuit package models. In one embodiment, each of the plurality of package models contains information descriptive of a distinct package. Such information may include, for example, intra-package path lengths and/or propagation delays of signal nets in the modeled packages. Techniques are disclosed for automatically synthesizing such information to produce, for example, aggregate path lengths and/or propagation delays of the signal nets across all of the modeled packages. Such synthesis may be performed even when the package models use mutually inconsistent signal net naming conventions and the modeled packages are composed of different materials. Techniques are also disclosed for providing information to the package designer to assist the package designer in improving the design of the package models.

US Patent:

6769102, Jul 27, 2004

Filed:

Jul 19, 2002

Appl. No.:

10/199127

Inventors:

Mark D. Frank - Longmont CO
Jerimy Nelson - Ft. Collins CO
Peter Shaw Moldauer - Wellington CO

Assignee:

Hewlett-Packard Development Company - Houston TX

International Classification:

G06F 1750

US Classification:

716 5, 716 4, 716 1

Abstract:

Techniques are disclosed for verifying the proximity of signal return paths (e. g. , ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

US Patent:

6807657, Oct 19, 2004

Filed:

Jul 19, 2002

Appl. No.:

10/199331

Inventors:

Mark D. Frank - Longmont CO
Jerimy Nelson - Ft. Collins CO
Peter Shaw Moldauer - Wellington CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 5, 716 4, 716 11, 703 15

Abstract:

In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.

US Patent:

6845492, Jan 18, 2005

Filed:

Feb 13, 2003

Appl. No.:

10/365831

Inventors:

Mark D. Frank - Longmont CO, US
Jerimy C. Nelson - Ft. Collins CO, US
Karl J. Bois - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 2, 361762, 174266, 716 1, 716 6, 716 9, 716 19

Abstract:

A computer-implemented method for adjusting signal via impedance includes identifying a signal via in a circuit design database. The signal via is flagged as having an impedance error. A window is established around the signal via, with the window lying on a single layer. Only vias in the window may be adjusted to minimize the impedance error. At least one via in the window is adjusted to minimize said impedance error.

US Patent:

6859915, Feb 22, 2005

Filed:

Feb 13, 2003

Appl. No.:

10/365848

Inventors:

Mark D. Frank - Longmont CO, US
Jerimy C. Nelson - Fort Collins CO, US
Karl J. Bois - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 5

Abstract:

A computer-implemented method for verifying impedance of a signal line in an electrical circuit layout includes reading a desired impedance value for a signal line and identifying the signal line in a circuit design database. A window is established around the signal line in which circuit elements will be included in an impedance calculation for the signal line. The impedance of the signal line is calculated based on the circuit elements inside the window. The signal line is flagged if the calculated impedance differs from the desired impedance value.

US Patent:

6889367, May 3, 2005

Filed:

Feb 13, 2003

Appl. No.:

10/366205

Inventors:

Mark D. Frank - Longmont CO, US
Jerimy C. Nelson - Fort Collins CO, US
Karl J. Bois - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 1, 716 5, 716 4

Abstract:

A computer-implemented method is disclosed for verifying impedance in a differential via pair. A target differential via pair is identified in a design database. A desired modal characteristic impedance for the target differential via pair is obtained. A two-dimensional window is established around the differential via pair in which neighboring vias will be included in a modal characteristic impedance calculation for the target differential via pair. A modal characteristic impedance for the target differential via pair is calculated based at least in part on the neighboring vias in the two-dimensional window. The target differential via pair is flagged if the calculated modal characteristic impedance does not match the desired modal characteristic impedance.

US Patent:

6907589, Jun 14, 2005

Filed:

Feb 19, 2003

Appl. No.:

10/368988

Inventors:

Mark D. Frank - Longmont CO, US
Jerimy Nelson - Fort Collins CO, US
Nathan Bertrand - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 5

Abstract:

A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e. g. , via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.

US Patent:

6922822, Jul 26, 2005

Filed:

Jul 19, 2002

Appl. No.:

10/199668

Inventors:

Mark D. Frank - Longmont CO, US
Jerimy Nelson - Ft. Collins CO, US
Peter Shaw Moldauer - Wellington CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 4, 716 5

Abstract:

Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.