Mark W French

US Patent:

8059128, Nov 15, 2011

Filed:

Apr 19, 2006

Appl. No.:

11/407464

Inventors:

Justin S. Legakis - Sunnyvale CA, US
Mark J. French - Raleigh NC, US
Steven E. Molnar - Chapel Hill NC, US
Lukito Muliadi - San Jose CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 15/80
G06F 21/00

US Classification:

345505, 345530, 345543, 711168

Abstract:

A method of performing a blit operation in a parallel processing system includes dividing a blit operation into batches of pixels, performing reads of pixels associated with a first batch in any order, confirming that all reads of pixels associated with the first batch are completed, and performing writes of pixels associated with the first batch in any order. The pixels of the first batch and pixels of additional batches are applied to parallel processors, where the parallel processors include a corral defined by entry points and exit points distributed across the parallel processors.