Mark I Gardner

US Patent:

6355955, Mar 12, 2002

Filed:

Feb 14, 2000

Appl. No.:

09/503979

Inventors:

Mark I. Gardner - Cedar Creek TX
H. Jim Fulford - Austin TX
Daniel Kadosh - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257330, 257408

Abstract:

An integrated circuit fabrication process is provided for forming a transistor having shallow effective source/drain regions and/or laterally shortened source/drain regions. In one embodiment a mesa is formed from the semiconductor substrate. The mesa preferably extends from an upper surface of the semiconductor substrate. A gate conductor is preferably formed on a dielectric layer which is formed on an upper surface of the mesa. LDD areas and source/drain regions are formed such that the regions are substantially contained within the mesa. In another embodiment, a gate conductor material is deposited within a trench, the trench being lined with a gate dielectric material, formed in a semiconductor substrate. The deposited gate conductor material is etched to form a gate conductor in which a lower surface of the gate conductor is substantially below an upper surface of the silicon substrate. Source/drain regions are formed within the semiconductor substrate such that the effective depth of the formed source/drain regions is minimized.

US Patent:

6358828, Mar 19, 2002

Filed:

Jul 17, 1998

Appl. No.:

09/118514

Inventors:

Daniel Kadosh - Austin TX
Mark I. Gardner - Cedar Creek TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438586, 438152, 438197, 257 67, 257 69, 257508

Abstract:

A three-dimensional integrated circuit and fabrication process is provided for producing active and passive devices on various levels of the integrated circuit. The present process is particularly suited to interconnecting a source of one transistor to a drain of another to form series-connected transistors often employed in core logic units. A junction of an underlying transistor can be connected to a junction of an overlying transistor, with both transistors separated by an interlevel dielectric. The lower transistor junction is connected to the upper level transistor junction using a plug conductor. The plug conductor and, more specifically, the mutually connected junction, is further coupled to a laterally extended interconnect. The interconnect extends from the mutual connection point of the plug conductor to a substrate of the overlying transistor. Accordingly, the source and substrate of the overlying transistor can be connected to a drain of the underlying transistor to not only achieve series-connection but also to connect the source and substrate of an internally configured transistor for the purpose of reducing body effects.

US Patent:

6362510, Mar 26, 2002

Filed:

Dec 7, 1998

Appl. No.:

09/206550

Inventors:

Mark I. Gardner - Cedar Creek TX
Charles E. May - Gresham OR

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257374, 257602, 257610, 257647

Abstract:

A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.

US Patent:

6365943, Apr 2, 2002

Filed:

Sep 21, 1998

Appl. No.:

09/157644

Inventors:

Mark I. Gardner - Cedar Creek TX
Daniel Kadosh - Austin TX
Fred N. Hause - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257377, 257382, 257347

Abstract:

A semiconductor transistor which includes a silicon base layer, a gate dielectric formed on the silicon base layer, first and second silicon source/drain structures, first and second spacer structures, and a silicon gate structure is provided. A method for forming the semiconductor transistor may include a semiconductor process in which a dielectric layer is formed on an upper surface of a semiconductor substrate which includes a silicon base layer. Thereafter, an upper silicon layer is formed on an upper surface of the dielectric layer. The dielectric layer and the upper silicon layer are then patterned to form first and second silicon-dielectric stacks on the upper surface of the base silicon layer. The first and second silicon-dielectric stacks are laterally displaced on either side of a channel region of the silicon substrate and each include a proximal sidewall and a distal sidewall. The proximal sidewalls are approximately coincident with respective boundaries of the channel region.

US Patent:

6372588, Apr 16, 2002

Filed:

Apr 21, 1997

Appl. No.:

08/837523

Inventors:

Derick J. Wristers - Austin TX
Robert Dawson - Austin TX
Mark I. Gardner - Cedar Creek TX
Frederick N. Hause - Austin TX
Mark W. Michael - Cedar Park TX
Bradley T. Moore - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438303, 438564

Abstract:

A method of making an IGFET using solid phase diffusion is disclosed. The method includes providing a device region in a semiconductor substrate, forming a gate insulator on the device region, forming a gate on the gate insulator, forming an insulating layer over the gate and the device region, forming a heavily doped diffusion source layer over the insulating layer, and driving a dopant from the diffusion source layer through the insulating layer into the gate and the device region by solid phase diffusion, thereby heavily doping the gate and forming a heavily doped source and drain in the device region. Preferably, the gate and diffusion source layer are polysilicon, the gate insulator and insulating layer are silicon dioxide, the dopant is boron or boron species, and the dopant provides essentially all P-type doping for the gate, source and drain, thereby providing shallow channel junctions and reducing or eliminating boron penetration from the gate into the substrate.

US Patent:

6373113, Apr 16, 2002

Filed:

May 6, 1998

Appl. No.:

09/073755

Inventors:

Mark I. Gardner - Cedar Creek TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2976

US Classification:

257411, 257410, 257412, 257344, 257369

Abstract:

An integrated circuit is provided in which nitrogen is incorporated into the gate dielectric and transistor gate. A method for forming the integrated circuit preferably comprises the providing of a semiconductor substrate that has a p-well and a laterally displaced n-well, each including a channel region laterally displaced between a pair of source/drain regions. Preferably, the semiconductor substrate has a resistivity of approximately 10 to 15 -cm. A dielectric layer is formed on an upper surface of the semiconductor substrate. The formation of the dielectric layer preferably comprises a thermal oxidation performed at a temperature of approximately 600 to 900Â C. and the resulting thermal oxide has a thickness less than approximately 50 angstroms. A conductive gate layer is then formed on the dielectric layer. In a preferred embodiment, the conductive gate layer is formed by chemically vapor depositing polysilicon at a pressure of less than approximately 2 torrs at a temperature in the range of approximately 500 to 650Â C.

US Patent:

6380055, Apr 30, 2002

Filed:

Oct 22, 1998

Appl. No.:

09/177043

Inventors:

Mark I. Gardner - Cedar Creek TX
Robert Dawson - Austin TX
Frederick N. Hause - Austin TX
Mark W. Michael - Cedar Park TX
Bradley T. Moore - Austin TX
Derick J. Wristers - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438585, 438560, 438592

Abstract:

A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 thick.

US Patent:

6380554, Apr 30, 2002

Filed:

Jun 8, 1998

Appl. No.:

09/093358

Inventors:

John J. Bush - Leander TX
Mark I. Gardner - Cedar Creek TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2358

US Classification:

257 48, 257758

Abstract:

The present invention advantageously provides a test structure and method for using electrical measurements to determine the overlay between successive layers of conductors lithographically patterned upon a semiconductor topography. According to an embodiment, a test structure is provided which includes first, second, and third conductive structures having first, second, and third corner regions, respectively. Alternatively, the conductive structures may include only a single conductive structure having three corner regions. Each corner region is bounded by a pair of outer lateral edges configured substantially perpendicular to one another. First, second, and third conductors are operably coupled to the first, second, and third corner regions, respectively, such that overlapping areas of the conductors arranged directly above the corner regions are substantially rectangular in shape. The layout design for the test structure specifies the targeted dimensions, x and y, of each overlapping area. Fabrication of the test structure may result in the overlapping areas being shifted from their targeted positions such that their dimensions are larger or smaller than their targeted values.