Mark Alan Gilmer

Address:

1507 Highpointe Grn, Spring, TX 77379

VIN:

JTMZD33V185091203

Make:

TOYOTA

Model:

RAV4

Year:

2008

US Patent:

61724076, Jan 9, 2001

Filed:

Apr 16, 1998

Appl. No.:

9/061552

Inventors:

Mark I. Gardner - Cedar Park TX
Mark C. Gilmer - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2972

US Classification:

257410

Abstract:

An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide. In an alternative embodiment, the gate dielectric may be formed sufficiently thick such that sidewall spacers are unnecessary to prevent silicide bridging between the gate conductor and the junction regions. In another alternative embodiment, the lightly doped drain implant areas may be formed self-aligned to the gate electrode prior to spacer formation.

US Patent:

58513078, Dec 22, 1998

Filed:

Apr 28, 1997

Appl. No.:

8/842092

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX
Robert Paiz - Austin TX

Assignee:

Advanced Micro Devices, Inc.

International Classification:

B08B 900

US Classification:

134 221

Abstract:

A method for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.

US Patent:

59045426, May 18, 1999

Filed:

Mar 26, 1997

Appl. No.:

8/825015

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX
Thomas E. Spikes - Round Rock TX

Assignee:

Advanced Micro Devices, Inc.

International Classification:

H01L21/76

US Classification:

438439

Abstract:

An in situ process is provided for isolating semiconductor devices according to a LOCOS process. The invention contemplates performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth all within a single chamber without removing the wafers from the chamber during processing. The invention is believed to result in increased yields and process throughput by reducing the exposure of the wafers to outer-chamber contaminants, thermal stress, and transportation damage, as well as reducing inter-chamber transportation time. The invention also contemplates an in situ processing chamber adapted for performing field oxide growth, nitride layer removal, sacrificial oxide growth and removal, and gate oxide growth as part of a LOCOS isolation process. The in situ processing chamber is adapted for thermal oxidation and etching processes to implement the LOCOS isolation structure. A conventional oxidation furnace may be adapted to provide the in situ processing chamber by adapting the oxidation furnace to accept etchant gasses.

US Patent:

59857064, Nov 16, 1999

Filed:

May 8, 1997

Appl. No.:

8/853499

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218238

US Classification:

438199

Abstract:

A semiconductor process in which an initial gate dielectric layer is formed on an upper surface of a semiconductor substrate. The initial gate dielectric layer is polished with a chemical mechanical polish to produce a finished gate dielectric layer. A thickness of the finished gate dielectric layer is less than a thickness of the initial gate dielectric layer and the thickness of the preferred finished gate dielectric layer is in the range of approximately 25 to 60 angstroms. In one embodiment, the initial gate dielectric layer is formed by thermally oxidizing the semiconductor substrate in an oxygen bearing ambient maintained at a temperature in the range of approximately 600. degree. C. to 900. degree. C. In an alternative embodiment, the formation of the initial gate dielectric layer is achieved by depositing an oxide. In this embodiment, the deposited oxide is preferably fabricated by a chemical vapor deposition process using a TEOS source in a CVD reactor chamber maintained at a temperature in the range of approximately 300. degree. C. to 600. degree. C.

US Patent:

61488321, Nov 21, 2000

Filed:

Sep 2, 1998

Appl. No.:

9/145606

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX
Robert Paiz - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B08B 302
B08B 900

US Classification:

134166R

Abstract:

An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.

US Patent:

61066184, Aug 22, 2000

Filed:

Jun 1, 1998

Appl. No.:

9/088783

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B05C 1102
B05C 1300
B05C 906
B05B 302

US Classification:

118 52

Abstract:

Apparatus and method for depositing fluids on both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel and that is operable to rotate the mandrel. The apparatus also includes means for dispensing a first volume of fluid on the semiconductor wafer and a second volume of fluid on the semiconductor wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel. The mandrel is rotated to spin the semiconductor wafer and a semiconductor processing fluid is sprayed on the first and second sides of the semiconductor wafer.

US Patent:

58496432, Dec 15, 1998

Filed:

May 23, 1997

Appl. No.:

8/862516

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX
Daniel Kadosh - Austin TX

Assignee:

Advanced Micro Devices, Inc.

International Classification:

H01L 21306

US Classification:

438773

Abstract:

A method of growing an oxide film in which the upper surface of a semiconductor substrate is cleaned and the semiconductor substrate is dipped into an acidic solution to remove any native oxide from the upper surface. The substrate is then directly transferred from the acidic solution to an oxidation chamber. The oxidation chamber initially contains an inert ambient maintained at a temperature of less than approximately 500. degree. C. The transfer is accomplished without substantially exposing the substrate to oxygen thereby preventing the formation of a native oxide film on the upper surface of the substrate. Thereafter, a fluorine terminated upper surface is formed on the semiconductor substrate. The temperature within the chamber is then ramped from the first temperature to a second or oxidizing temperature if approximately 700. degree. C. to 850. degree. C. The presence of the fluorine terminated upper surface substantially prevents oxidation of the semiconductor substrate during the temperature ramp.

US Patent:

58211721, Oct 13, 1998

Filed:

Jan 6, 1997

Appl. No.:

8/779264

Inventors:

Mark C. Gilmer - Austin TX
Mark I. Gardner - Cedar Creek TX

Assignee:

Advanced Micro Devices, Inc.

International Classification:

H01L 21322

US Classification:

438769

Abstract:

A semiconductor manufacturing process in which a single crystal silicon semiconductor substrate is immersed in an oxidation chamber maintained at a first temperature preferably between 400. degree. and 700. degree. C. for a first duration. During the first duration, the oxidation chamber comprises a first ambient gas of N. sub. 2 or Argon. Thereafter, the ambient temperature within the oxidation chamber is ramped to a second temperature in the range of approximately 600. degree. to 1100. degree. C. NH. sub. 3 is then introduced into the oxidation chamber simultaneously with either NO or N. sub. 2 O to form an oxynitride layer. Thereafter, a conductive gate structure is formed on the oxynitride layer and a source/drain impurity distribution is introduced into a pair of source/drain regions laterally displaced on either side of the channel region of the semiconductor substrate. The channel region is aligned with the conductive gate. Preferably, the resistivity of an epitaxial layer of the semiconductor substrate is in the range of approximately 10 to 15. OMEGA. -cm.