Mark Joseph Good

US Patent:

6495475, Dec 17, 2002

Filed:

Mar 28, 2001

Appl. No.:

09/821365

Inventors:

Mark A. Good - Colorado Springs CO
Amit S. Kelkar - Castle Rock CO

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H01L 21469

US Classification:

438773, 438787

Abstract:

A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide-layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a temporary silicon dioxide layer. The temporary silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.

US Patent:

6709990, Mar 23, 2004

Filed:

Oct 9, 2002

Appl. No.:

10/267354

Inventors:

Mark A. Good - Colorado Springs CO
Amit S. Kelkar - Castle Rock CO

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H01L 21469

US Classification:

438773, 438758, 438778, 438780, 438787, 438791, 438745, 438756, 438757, 438790

Abstract:

A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.

US Patent:

7629649, Dec 8, 2009

Filed:

May 9, 2006

Appl. No.:

11/382455

Inventors:

Gayle W. Miller - Colorado Springs CO, US
Thomas S. Moss - Colorado Springs CO, US
Mark A. Good - Colorado Springs CO, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H01L 21/331

US Classification:

257347, 257607, 257E21567, 257E29287, 438311

Abstract:

Methods and materials for silicon on insulator wafer production in which the doping concentration in a handle wafer is sufficiently high to inhibit dopant from diffusing from the bond wafer during or after bonding to the handle wafer.

US Patent:

20080069952, Mar 20, 2008

Filed:

Sep 18, 2006

Appl. No.:

11/532850

Inventors:

Thomas S. Moss - Colorado Springs CO, US
Mark A. Good - Colorado Springs CO, US

Assignee:

ATMEL CORPORATION - San Jose CA

International Classification:

C23C 16/00

US Classification:

4272481, 4272554

Abstract:

A method of cleaning and oxidizing a substrate, for example, a silicon wafer, and forming a film (e.g., silicon dioxide) in-situ by placing the substrate in a chamber, pumping-down the chamber to a predetermined subatmospheric pressure, and elevating a temperature of the substrate within the chamber. Cleaning begins by releasing hydrogen gas into the chamber for a time period of, for example, 5 seconds to 300 seconds. The hydrogen gas, along with any contaminants, are then evacuated from the chamber. Prior to removing the substrate, an oxidant, such as oxygen (O), steam or another process (e.g., an in-situ steam generation (ISSG) process) is then released into the chamber and the film is formed on a surface of the substrate.

US Patent:

20080286967, Nov 20, 2008

Filed:

May 18, 2007

Appl. No.:

11/750485

Inventors:

Mark A. Good - Colorado Springs CO, US
Craig Schwechel - Glen Allen VA, US

Assignee:

Atmel Corporation - San Jose CA

International Classification:

H01L 21/44

US Classification:

438671, 438669, 257E21476

Abstract:

A method of forming an electrical contact between an active semiconductor device layer and a base substrate. The method includes forming a first masking layer over an uppermost surface of the active semiconductor layer, patterning a window in the masking layer, and etching an opening down to the base substrate within an area defined by the window. The opening is filled with a semiconductor contact material while simultaneously adding a dopant to the semiconductor contact material thereby forming an electrical contact between the active semiconductor device layer and the base substrate.

US Patent:

20090189159, Jul 30, 2009

Filed:

Jan 28, 2008

Appl. No.:

12/020930

Inventors:

Darwin Enicks - Colorado Springs CO, US
Mark Good - Colorado Springs CO, US
John Chaffee - Colorado Springs CO, US

Assignee:

ATMEL CORPORATION - San Jose CA

International Classification:

H01L 29/04
H01L 21/322

US Classification:

257 63, 438473, 257E21317, 257E29003

Abstract:

Disclosed herein are devices, methods and systems for implementing gettering layers. Devices including gettering layers can be implemented such that a gettering layer doped with carbon, boron, fluorine or any other appropriate impurity is formed on a semiconductor substrate, a device layer is formed on the gettering layer, and a device region is formed in the device layer having a depth that maintains a distance in the device layer between the gettering layer and the device region.

US Patent:

20100019306, Jan 28, 2010

Filed:

Sep 26, 2008

Appl. No.:

12/239504

Inventors:

Bohumil Lojek - Colorado Springs CO, US
Mark A. Good - Colorado Springs CO, US
Philip O. Smith - Colorado Springs CO, US

Assignee:

ATMEL Corporation - San Jose CA

International Classification:

H01L 21/8247
H01L 21/322

US Classification:

257316, 438473, 257E2168

Abstract:

This document discloses devices fabricated on a semiconductor substrate and methods of fabricating the same. The devices can be memory cells having a tunnel window that is defined by dry-etching oxide to expose the semiconductor substrate and growing a tunnel oxide layer on the exposed semiconductor substrate. The semiconductor substrate can be decontaminated and/or repaired by exposing the semiconductor substrate to an optical irradiated energy source having a predefined energy that is sufficient to break molecular bonds of the contaminants and exposing the semiconductor substrate to a temperature that is sufficient to recrystallize the crystal lattice of the substrate.

Address:

6675 Sky Hawk Ct, Colorado Springs, CO 80919

Phone:

7195949324

VIN:

JTEDC3EH9B2000722

Make:

TOYOTA

Model:

HIGHLANDER HYBRID

Year:

2011