Mark David Greenberg

US Patent:

60880937, Jul 11, 2000

Filed:

Oct 6, 1997

Appl. No.:

8/944779

Inventors:

Mark Greenberg - Santa Ana CA

International Classification:

G01N 2100
G01B 1130

US Classification:

3562373

Abstract:

A method for surfacing panels, such as automobile panels or the like, includes the steps of applying a thin, reflective, flexible sheet to a panel to be surfaced, illuminating the sheet and comparing differing levels of brightness on the sheet in order to identify irregularities in the panel underlying the sheet. Thereafter, removing portions of the sheet that are overlying the identified irregularities in order to expose irregular portions of the panel, correcting the identified irregular portions and removing a remaining portions of the sheet from the corrected panel.

US Patent:

57098263, Jan 20, 1998

Filed:

Oct 4, 1996

Appl. No.:

8/726389

Inventors:

Mark Greenberg - Santa Ana CA

Assignee:

Olaf Haas - Mission Viejo CA

International Classification:

B29C 7302
G01B 1130

US Classification:

264 401

Abstract:

A method for surfacing panels, such as automobile panels or the like, includes the steps of applying a thin, reflective, flexible sheet to a panel to be surfaced, illuminating the sheet and comparing differing levels of brightness on the sheet in order to identify irregularities in the panel underlying the sheet. Thereafter, removing portions of the sheet that are overlying the identified irregularities in order to expose irregular portions of the panel, correcting the identified irregular portions and removing a remaining portion of the sheet from the corrected panel.

US Patent:

20200402287, Dec 24, 2020

Filed:

Aug 12, 2019

Appl. No.:

16/538819

Inventors:

- Suwon-si, KR
Mark GREENBERG - Austin TX, US

International Classification:

G06T 15/00
G06F 11/34
G06F 9/30
G06F 9/355
G06F 9/38
G06F 9/48

Abstract:

A shader core includes a first processing element (PE), a second processing element, a register file and a warp sequencing unit. The first PE includes a first predetermined number of execution units, and the second PE includes a second predetermined number of execution units in which the second predetermined number of execution units is less than the first predetermined number of execution units. The register file shared by the first PE and the second PE. The warp sequencer unit (WSQ) is coupled to the first PE and to the second PE and schedules an instruction trace to execute on the first PE or the second PE based on information contained in a trace header of the instruction trace. The information contained in the trace header indicates whether the instruction trace is executable on the second PE.

US Patent:

20180246720, Aug 30, 2018

Filed:

Feb 24, 2017

Appl. No.:

15/441411

Inventors:

- Redwood City CA, US
Nathan Sheeley - Austin TX, US
Mark Greenberg - Austin TX, US
Matthew Smittle - Allen TX, US
Paul Jordan - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38

Abstract:

An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.