Mark D Matson

US Patent:

6360241, Mar 19, 2002

Filed:

Apr 20, 1999

Appl. No.:

09/294597

Inventors:

Mark D. Matson - Acton MA
Robert J. Dupcak - Framingham MA
Jonathan D. Krause - Marlboro MA
Sridhar Samudrala - Westboro MA

Assignee:

Compaq Information Technologies Goup, L.P. - Houston TX

International Classification:

B06F 700

US Classification:

708493, 708650

Abstract:

The invention provides computer apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

US Patent:

6366942, Apr 2, 2002

Filed:

Mar 30, 1999

Appl. No.:

09/281501

Inventors:

Roy W. Badeau - Berlin MA
William Robert Grundmann - Hudson MA
Mark D. Matson - Acton MA
Sridhar Samudrala - Westboro MA

Assignee:

Compaq Information Technologies Group LP - Houston TX

International Classification:

G06F 750

US Classification:

708497

Abstract:

A method and apparatus for operating on floating point numbers is provided that accepts two floating point numbers as operands in order to perform addition, a rounding adder circuit is provided which can accept the operands and a rounding increment bit at various bit positions. The circuit uses full adders at required bit positions to accommodate a bit from each operand and the rounding bit. Since the proper position in which the rounding bit should be injected into the addition may be unknown at the start, respective low and high increment bit addition circuits are provided to compute a result for both a low and a high increment rounding bit condition. The final result is selected based upon the most significant bit of the low rounding bit increment result. In this manner, the present rounding adder circuit eliminates the need to perform a no increment calculation used to select a result, as in the prior art. Through the use of full adders, the circuit not only accounts for the round increment bit, but can accept increment bits at any bit position to perform operations such as twos complement, thus further reducing the operations required to perform a desired floating point mathematical operation.

US Patent:

6400186, Jun 4, 2002

Filed:

Apr 21, 1999

Appl. No.:

09/296013

Inventors:

Daniel W. Bailey - Northborough MA
Mark D. Matson - Acton MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G01R 1900

US Classification:

327 55, 327 57, 327198, 365208, 36518911

Abstract:

Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifiers performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

US Patent:

6414520, Jul 2, 2002

Filed:

Feb 1, 1999

Appl. No.:

09/241496

Inventors:

Robert J. Dupcak - Framingham MA
Randy L. Allmon - Hopedale MA
Mark D. Matson - Acton MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G01R 1900

US Classification:

327 52, 327 57, 365205, 365208

Abstract:

A sense amplifier for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.

US Patent:

6480036, Nov 12, 2002

Filed:

Nov 12, 2001

Appl. No.:

09/992850

Inventors:

Daniel W. Bailey - Northborough MA
Mark D. Matson - Acton MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G01R 1900

US Classification:

327 55, 327 57, 327198, 365208, 36518911

Abstract:

A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifiers performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

US Patent:

6564239, May 13, 2003

Filed:

Dec 14, 2001

Appl. No.:

10/016902

Inventors:

Mark D. Matson - Acton MA
Robert J. Dupcak - Framingham MA
Jonathan D. Krause - Marlboro MA
Sridhar Samudrala - Westboro MA

Assignee:

Hewlett-Packard Development Company L.P. - Houston TX

International Classification:

G06F 738

US Classification:

708605, 708650

Abstract:

Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix- or radix- signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.

US Patent:

6653869, Nov 25, 2003

Filed:

Feb 15, 2002

Appl. No.:

10/077194

Inventors:

Robert J. Dupcak - Framingham MA
Randy L. Allmon - Hopedale MA
Mark D. Matson - Acton MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R 1900

US Classification:

327 52, 327 57, 365207

Abstract:

A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

US Patent:

6779012, Aug 17, 2004

Filed:

Apr 18, 2003

Appl. No.:

10/419454

Inventors:

Mark D. Matson - Acton MA
Robert J. Dupcak - Framingham MA
Jonathan D. Krause - Marlboro MA
Sridhar Samudrala - Westboro MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 7552

US Classification:

708500

Abstract:

Computer method and apparatus for performing a square root or division operation generating a root or quotient. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.