Nvidia Jul 2001 - Oct 2017
System Architect
Nvidia Jul 2001 - Oct 2017
Senior Manager, Infrastructure Engineering
Education:
University of North Carolina at Chapel Hill 1992 - 2001
Doctorates, Doctor of Philosophy, Computer Science
University of North Carolina at Chapel Hill 1990 - 1992
Masters, Computer Science
North Carolina State University 1984 - 1989
Bachelors, Bachelor of Science, Computer Science
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/66
US Classification:
370461, 370463, 370412, 370419
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Performing Network Processing Functions
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/28
US Classification:
370392, 370465, 370401
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Internet Protocol (Ip) Router Residing In A Processor Chipset
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/43
US Classification:
370461, 370463, 370412, 370419
Abstract:
A novel network architecture that integrates the functions of an Internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Performing Network Processing Functions
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/28
US Classification:
370392, 370401, 370465
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Performing Network Processing Functions
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/54
US Classification:
370429
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Network Processing Pipeline Chipset For Routing And Host Packet Processing
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 12/54
US Classification:
370429, 370463, 711118, 712228
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Method And Apparatus For Performing Network Processing Functions
Robert A. Alfieri - Chapel Hill NC, US Gary D. Hicok - Mesa AZ, US Paul J. Sidenblad - Cupertino CA, US Mark A. Parris - Durham NC, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04L 9/34
US Classification:
713181, 713161
Abstract:
A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer's chipset such that the host computer's resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.
Mexico (mostly)Manager, Advanced Manufacturing Engineering at Gab... Past: Site Manager at ArvinMeritor, Manager, Advanced Manufacturing Engineering at ArvinMeritor... A proven leader with extensive multi-national manufacturing and business development experience. An experienced manufacturing professional with full P&L... A proven leader with extensive multi-national manufacturing and business development experience. An experienced manufacturing professional with full P&L responsibility for the areas of: operations, site management, project management, manufacturing, engineering, and sales. Experienced manager of...
Elizabeth Congdon, Gerald Reese, Christina Baker, Tina Armes, Jeff Futrell, Kimberly Killey, Stephanie Peanut, Verne Thompson, Paul Herman, Peter Morgan, Timothy Walley
The other non-executive directors include James Leng, Sir Graham Hearne, George Rose and Mark Parris. A further two Independent non-executive Directors are expected to be appointed with effect from the completion of the merger.