Mark J Pavicic

US Patent:

6816102, Nov 9, 2004

Filed:

Jun 20, 2003

Appl. No.:

10/600319

Inventors:

Mark J. Pavicic - Fargo ND

Assignee:

Dakota Technologies, Inc. - Fargo ND

International Classification:

H03M 112

US Classification:

341155, 341122, 341166

Abstract:

An apparatus for capturing and digitizing at least one analog signal derived from an event with a signal duration that is short compared to the interval between consecutive analog signals has two or more memories each capable of storing a sequence of analog samples of one of two or more analog signals derived from the event. There is a trigger for triggering the sampling and storage in the two or more memories of a sequence of analog samples to occur at about a 0. 5 gigahertz or higher rate and circuitry communicating with the memories for selectively initiating the read out of the analog samples in the memories. An analog to digital converter receives each analog sample read out from each of memories and produces from the analog samples corresponding digitized sample values. A digital signal processor controls parameters of the analog to digital converter and outputs the digitized sample values, such that the receiving and conversion and the output of digitized sample values is completed during the interval between consecutive analog signals.

US Patent:

6975251, Dec 13, 2005

Filed:

Aug 24, 2004

Appl. No.:

10/924405

Inventors:

Mark J. Pavicic - Fargo ND, US

Assignee:

Dakota Technologies, Inc. - Fargo ND

International Classification:

H03M007/00

US Classification:

341 50, 341122, 341155, 341166

Abstract:

An apparatus for capturing and digitizing a signal derived from an event has a memory for storing a sequence of analog samples from the signal derived from the event in a sampling operation occurring at about a 0. 5 gigahertz or higher sampling rate. Circuitry communicating with the memory selectively initiates the read out of the analog samples in the memories. An array of analog to digital converters receives a sequence of analog samples read out from the memory and produces from the analog samples a corresponding vector of digitized sample values. A waveform accumulator integrated with the array of analog to digital converters receives a vector of digitized sample values from a new waveform and combines these with a vector of digitized sample values from at least one prior waveform. An output stage outputs the vector of digitized sample values developed in the waveform accumulator.

US Patent:

7015484, Mar 21, 2006

Filed:

May 7, 2003

Appl. No.:

10/431347

Inventors:

Gregory Gillispie - Fargo ND, US
Mark J. Pavicic - Fargo ND, US

Assignee:

Dakota Technologies, Inc. - Fargo ND

International Classification:

G01N 21/64

US Classification:

2504581, 2504591

Abstract:

Apparatus and methods are provided for rapid and sensitive quantitative analysis of a sample's fluorescence decay properties. A repetitively pulsed excitation light source generates pulsed fluorescence in the sample. A fluorescence wavelength selector receives a portion of the pulsed fluorescence emanating from the sample and outputs fluorescence photons whose wavelengths lie within a specified wavelength range. A photodetector receives the fluorescence photons within the specified wavelength range as an input from the fluorescence wavelength selector and outputs a time-dependent electrical signal. An array of memory elements stores a representation of the time-dependent electrical signal as a time-series of analog voltages or charges. Successive elements in the array correspond to a time increment of no greater than 4 ns. An analog-to-digital converter transforms the time-series of analog voltages or charges into a corresponding digitized fluorescence waveform.

US Patent:

7956639, Jun 7, 2011

Filed:

Jul 23, 2009

Appl. No.:

12/508149

Inventors:

Mark J. Pavicic - Fargo ND, US
Chao You - West Fargo ND, US

Assignee:

NDSU Research Foundation - Fargo ND

International Classification:

H03K 19/173

US Classification:

326 38, 326 41

Abstract:

An apparatus and method controlling cellular automata containing a plurality of cascaded circuit cells having logic units. The cells are interleaved in groups toward supporting multiple directions, for example quad cells in which each cells of the quad is directed in a different directions separated by a fixed angle, such as 90 degrees (i. e. , north, east, south, and west). These cells are triggered asynchronously as each cell is stabilized in preparation for receiving the trigger. The cells process data selectively based on the configuration of the cell and in response to receipt of data and trigger (or combined data and trigger) conditions from neighboring cells. The array can be utilized within a wide range of digital logic. As there is no need for distributing a global clock across the array of cells, the size of the array can be extended to any desired dimension.

US Patent:

20050136448, Jun 23, 2005

Filed:

Sep 29, 2004

Appl. No.:

10/954942

Inventors:

Kirk Hartel - West Fargo ND, US
Mark Pavicic - Fargo ND, US
Gregory Gillispie - Fargo ND, US

Assignee:

Dakota Technologies, Inc. - Fargo ND

International Classification:

C12Q001/68
C12M001/34
G03C005/16

US Classification:

435006000, 435287200, 250581000

Abstract:

Apparatus and methods are provided to monitor hybridization of a probe polynucleotide for detection and analysis of a target polynucleotide in a test sample. A single-stranded probe polynucleotide is attached to an identifiable region on a substrate and allowed to hybridize to a complementary target polynucleotide that may be present in a test sample. A fluorophore noncovalently interacts with the double-stranded polynucleotides that may be formed. The fluorescence decay or lifetime of the fluorophore associated with the double-stranded polynucleotide is different from the fluorescence decay or lifetime of the fluorophore when it is associated with a single-stranded polynucleotide. The detection of double-stranded polynucleotides at a particular region is an indication that the target polynucleotide is present in the test sample.

US Patent:

20060134644, Jun 22, 2006

Filed:

Oct 28, 2004

Appl. No.:

10/977347

Inventors:

Kirk Hartel - West Fargo ND, US
Gregory Gillispie - Fargo ND, US
Mark Pavicic - Fargo ND, US

International Classification:

C12Q 1/68
C12M 1/34

US Classification:

435006000, 435287200

Abstract:

This invention relates to apparatus and methods to detect a target analyte in a test sample by forming a fluorescent complex comprising the target analyte and a probe. The fluorescence decay and/or lifetime changes upon complex formation. The apparatus includes a pulsed light source and a digitizer to measure fluorescent decay and/or lifetime of the fluorophore in the complex

US Patent:

20120007898, Jan 12, 2012

Filed:

Jul 15, 2011

Appl. No.:

13/184258

Inventors:

Mark J. Pavicic - Fargo ND, US

Assignee:

NDSU RESEARCH FOUNDATION - Fargo ND

International Classification:

G09G 5/10
G09G 3/36

US Classification:

345690, 345 87

Abstract:

An apparatus for controlling light emission and/or sensing in an array of optical elements. An infra-extensible array having a plurality of subarray display circuits interconnected with neighboring subarray display circuits. Each subarray display circuit is configured with a processor and a plurality of output and/or input elements. Messages and instructions can be propagated from one subarray display circuit to another to provide local processing relating to input and output elements, such as changing the pixels in the display from a subarray display circuit in response to locally sensed conditions or those communicated from neighboring subarray display circuits. Apparatus is infra-extensible as both the number of processors for executing display/sensor programming, and the number of communication channels available through which instructions can be received, increases automatically in response to increasing the number of subarray display circuits within the apparatus.

US Patent:

53923855, Feb 21, 1995

Filed:

May 22, 1992

Appl. No.:

7/888385

Inventors:

Carlo J. Evangelisti - Jefferson Valley NY
Leon Lumelsky - Stamford CT
Mark J. Pavicic - Fargo ND

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1562

US Classification:

395131

Abstract:

SIMD computer architecture is used in conjunction with a host processor and coordinate processor to render quality, three-dimensional, anti-aliased shaded color images into the frame buffer of a video display system. The method includes a parallel algorithm for rendering an important graphic primitive for accomplishing the production of a smoothly shaded color three-dimensional triangle with anti-aliased edges. By taking advantage of the SIMD architecture and said parallel algorithm, the very time consuming pixel by pixel computations are broken down for parallel execution. A single coordinate processor computes and transmits an overall triangle record which is essentially the same for all blocks of pixels within a given bounding box which box in turn surrounds each triangle. The individual pixel data is produced by a group of M. times. N pixel processors and stored in the frame buffer in a series of repetitive steps wherein each step corresponds to the processing of an M. times.