Mark D Redman

US Patent:

6757244, Jun 29, 2004

Filed:

Oct 1, 1998

Appl. No.:

09/164925

Inventors:

Mark D. Redman - Chandler AZ

Assignee:

Samsung Electronics Co., Ltd. - Suwon

International Classification:

G01R 3108

US Classification:

370227, 370366, 370434, 370442, 710100

Abstract:

There is disclosed, for use in a communication device, such as an access concentrator, that performs high-speed data transfers between a group of M data drivers and a group of N data receivers, a space and time division multiplexing (STDM) bus interface in which each bus line is a single source/multidrop line that connects the output of only one driver to multiple receivers (i. e. , a 1:N configuration). The disclosed invention minimizes the number of data reflections on each bus line by eliminating all but one of the stubs associated with the bus drivers. The disclosed device also eliminates a single point or failure situation. The bus interface also provides additional robustness by means of a âback-upâ bus line that is coupled to alternate outputs on all data drivers and to inputs on all receivers (i. e. , multisource/multidrop or M:N configuration).

US Patent:

6782007, Aug 24, 2004

Filed:

Jan 26, 1999

Appl. No.:

09/238003

Inventors:

Mark D. Redman - Chandler AZ

Assignee:

Samsung Electronics Co., Ltd. - Suwon

International Classification:

H04J 306

US Classification:

370509, 370510

Abstract:

There is disclosed a data transfer system that uses a TDM serial multiple format and supporting method that is capable of multiplexing and de-multiplexing a number of asynchronous and arbitrarily framed component serial data streams. The data transfer system comprises: 1) a frame data interface circuit capable of receiving incoming data streams from a plurality of asynchronous frame data sources and indicating their frame boundaries with the bit streams; and 2) a transmit buffer and data segmenter coupled to the frame data interface circuit and receiving the incoming data frames therefrom. The transmit buffer/segmenter divides incoming data frames into N-bit data fields and attaches to each N-bit data field an M-bit control field identifying the frame bit boundary and capable of conveying additional control or synchronization information associated with the incoming data frames. Each N-bit data field and the attached M-bit control field comprise a data record to be transmitted. The data records are assembled into a TDM transport formatted datagram consisting of, for example, 28 time slots, each of which is capable of carrying a single data record from a selected serial buffer/segmenter.

US Patent:

7185249, Feb 27, 2007

Filed:

Apr 30, 2002

Appl. No.:

10/135877

Inventors:

Thomas Tkacik - Phoeniz AZ, US
Jonathan Lutz - Kitchener, CA
Lawrence Case - Phoenix AZ, US
Douglas Hardy - Scottsdale AZ, US
Mark Redman - Gilbert AZ, US
Gregory Schmidt - Chandler AZ, US
Michael D. Fitzsimmons - Austin TX, US
Darrell L. Carder - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28
H03K 19/00

US Classification:

714726, 326 16

Abstract:

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

US Patent:

7401234, Jul 15, 2008

Filed:

Mar 1, 2004

Appl. No.:

10/791171

Inventors:

Lawrence L. Case - Phoenix AZ, US
Mark D. Redman - Gilbert AZ, US
Thomas E. Tkacik - Phoenix AZ, US
Joel D. Feldman - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 11/30

US Classification:

713193, 713153, 711100, 711170, 711137, 707 9, 717151

Abstract:

Methods and apparatus are provided for an electronic device having an autonomous memory checker for runtime security assurance. The autonomous memory checker comprises a controller, a memory reference file coupled to the controller, and an authentication engine coupled to the controller. A check is performed during runtime operation of the electronic device. The autonomous memory checker generates runtime reference values corresponding to trusted information stored in memory. The runtime reference values are compared against memory reference values stored in the memory reference file. The memory reference values are generated from the trusted information stored in memory. An error signal is generated when the runtime reference values are not identical to the memory reference values thereby indicating that the trusted information has been modified.

US Patent:

7725788, May 25, 2010

Filed:

Jan 25, 2007

Appl. No.:

11/627229

Inventors:

Thomas Tkacik - Phoenix AZ, US
Jonathan Lutz - Kitchner, CA
Lawrence Case - Fountain Hills AZ, US
Douglas Hardy - Scottsdale AZ, US
Mark Redman - Gilbert AZ, US
Gregory Schmidt - Chandler AZ, US
Steven Tugenberg - Scottsdale AZ, US
Michael D. Fitzsimmons - Austin TX, US
Darrell L. Carder - Dripping Springs TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28

US Classification:

714726

Abstract:

A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

US Patent:

8117642, Feb 14, 2012

Filed:

Mar 21, 2008

Appl. No.:

12/053502

Inventors:

Carlin R. Covey - Tempe AZ, US
Ronald B. Harvey - Mesa AZ, US
Mark D. Redman - Gilbert AZ, US
Thomas E. Tkacik - Phoenix AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 7/04
G06F 11/30

US Classification:

726 2, 713189

Abstract:

A computing device () includes a trusted execution environment (TEE) manager () that manages a switchover from non-trusted software () to trusted software (). The TEE manager () includes memory () configured to store password-bearing, immediate-operand instructions (). At the point of switching between the non-trusted software () and the trusted software () the memory () may be accessed as instruction fetches, and its contents fetched into a CPU core () as instructions. Immediate-operand portions () of the immediate-operand instructions () provide passwords, which are written back into guess registers () within the TEE manager (). When a predetermined relationship between the instructions () and guesses in guess registers () is identified, actual execution of the immediate-operand instructions () is verified, the TEE mode of operation is signaled, and security-sensitive hardware () is enabled for use by a privileged routine () portion of the trusted software ().

US Patent:

8332641, Dec 11, 2012

Filed:

Jan 30, 2009

Appl. No.:

12/363259

Inventors:

Lawrence L. Case - Austin TX, US
Asaf Ashkenazi - Austin TX, US
Ruchir Chhabra - Austin TX, US
Carlin R. Covey - Tempe AZ, US
David H. Hartley - Seacombe Heights, AU
Troy E. Mackie - Austin TX, US
Alistair N. Muir - Austin TX, US
Mark D. Redman - Gilbert AZ, US
Thomas E. Tkacik - Phoenix AZ, US
John J. Vaglica - Austin TX, US
Rodney D. Ziolkowski - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 9/00

US Classification:

713168, 713182, 713185, 726 2

Abstract:

Under the direction of a first party, an integrated circuit (IC) device is configured to temporarily enable access to a debug interface of the IC device via authentication of the first party by a challenge/response process using a key of the IC device and a challenge value generated at the IC device. The first party then may conduct a software evaluation of the IC device via the debug interface. In response to failing to identify an issue with the IC device from the software evaluation, the first party can permanently enable open access to the debug interface while authenticated and provide the IC device to a second party. Under the direction of the second party, a hardware evaluation of the IC device is conducted via the debug interface that was permanently opened by the first party.

US Patent:

46202242, Oct 28, 1986

Filed:

Apr 3, 1985

Appl. No.:

6/719200

Inventors:

Mark D. Redman - Clarksburg MD

Assignee:

Communications Satellite Corp. - Washington DC

International Classification:

H04K 100
H04N 716
H04N 7167

US Classification:

358119

Abstract:

A method for scrambling a television signal for use with a multiplexed analog component (MAC) format employs a three digital bit code for each horizontal line of the picture. The bits identify the position of the luminance and chrominance information of the signal for every line of the television picture and whether the information is to be scanned from left to right or right to left.