Mark Kenneth Schneider

US Patent:

56939817, Dec 2, 1997

Filed:

Oct 17, 1995

Appl. No.:

8/544284

Inventors:

Mark R. Schneider - San Jose CA
Joseph Joroski - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2334
H05K 720

US Classification:

257718

Abstract:

Method of cooling electronic systems and semiconductor devices as well as an electronic system and a semiconductor device with heat dissipating elements. The method includes the steps of providing an electronic system or a semiconductor device with a heat sink including at least a first element having a generally flat shape with a shoulder projecting from one generally flat surface, and configured to thermally engage similar elements. In one embodiment, a first and a second heat sink element are provided, with one of the first and second elements having a protrusion and the other of the first and second elements defining a depression configured to receive and retain said protrusion. Alternatively, the first and second elements may be bonded together with a thermally conductive adhesive.

US Patent:

58888470, Mar 30, 1999

Filed:

Dec 8, 1995

Appl. No.:

8/569501

Inventors:

Michael D. Rostoker - Boulder Creek CA
Mark R. Schneider - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2158
H01L 21603
H01L 21607

US Classification:

438108

Abstract:

A semiconductor die is mounted to a die receiving area, which is defined by inner ends of conductive leads to which the die is connected. The die is temporarily retained in a substantially fixed position relative to the die receiving area by various techniques for the purpose of permitting bond wires to be attached between the conductive leads and the die. Preferred techniques include employing a mechanical chuck, dispensing an adhesive between the die and its die receiving area, and forming an ultrasonic bond between the die and the die receiving area. Once electrical connections between the die and the conductive lines are formed, the die need not be retained in a fixed position, as the electrical connections will provide sufficient support for the die. Accordingly, conventional die attach techniques, which expose the semiconductor die to substantially elevated temperatures, are avoided. Further, dies so mounted, which are not firmly anchored in accordance with conventional the attach techniques, are not subjected to mechanical stresses resulting from a difference in die thermal expansion between the die and its die receiving area.

US Patent:

56545878, Aug 5, 1997

Filed:

Oct 24, 1995

Appl. No.:

8/547277

Inventors:

Mark Schneider - San Jose CA
Joseph Joroski - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2334

US Classification:

257718

Abstract:

A stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the button-like projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottommost fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.

US Patent:

54058082, Apr 11, 1995

Filed:

Oct 26, 1993

Appl. No.:

8/142674

Inventors:

Michael D. Rostoker - San Jose CA
Nicholas F. Pasch - Pacifica CA
Mark Schneider - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2160

US Classification:

437209

Abstract:

Improved thermal and/or electrostatic discharge characteristics are realized in cavity-type semiconductor device assemblies by filling the cavity with either a thermally conductive fluid and/or an arc suppressing gas, or combinations thereof. The interior of the cavity, including the die, leads extending into the cavity, and connections between the die and the leads may be coated to provide protection from corrosive and/or electrical characteristics of the cavity-filling fluid (liquid or gas). The fluid may be introduced through a hole in a lid sealing the cavity, and the cavity is filled sufficiently that the fluid is in contact with the die at various spatial orientations of the package. A thermally-conductive fluid substantially filling the cavity provides improved thermal conduction from the die to the package body without the mechanical stress problems (e. g. , thermally induced cracking) ordinarily associated with bonding solid materials to the die.

US Patent:

59637951, Oct 5, 1999

Filed:

Jun 25, 1996

Appl. No.:

8/670349

Inventors:

Mark R. Schneider - San Jose CA
Joseph Joroski - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 23367
H01L 2144

US Classification:

438122

Abstract:

Method of cooling electronic systems an semiconductor devices as well as an electronic system and a semiconductor device with heat dissipating elements. The method includes the steps of providing an electronic system or a semiconductor device with a heat sink including at least a first element having a generally flat shape with a shoulder projecting from one generally flat surface, and configured to thermally engage similar elements. In one embodiment, a first and a second heat sink element are provided, with one of the first and second elements having a protrusion and the other of the first and second elements defining a depression configured to receive and retain said protrusion. Alternatively, the first and second elements may be bonded together with a thermally conductive adhesive.

US Patent:

39478670, Mar 30, 1976

Filed:

Dec 21, 1970

Appl. No.:

5/099904

Inventors:

Edward F. Duffek - Cupertino CA
Ernest J. Funk - Cupertino CA
Alfred S. Jankowski - San Jose CA
Jack C. Lane - Saratoga CA
William L. Lehner - Los Altos Hills CA
Floyd F. Oliver - Los Altos CA
Mark R. Schneider - San Jose CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

H01L 2348

US Classification:

357 70

Abstract:

Semiconductor devices containing integrated circuits are attached directly to external package leads by pressing simultaneously a plurality of groups of leads against bonding pads on a plurality of face-up semiconductor dice and heating the composite structures. Solder bumps on the bonding pads contain hard pedestals which prevent the overlying leads from being pushed into the faces of the semiconductor devices while the solder on the solder bumps melts to form the bonds between the leads and the underlying semiconductor dice. The process for carrying out this operation lowers significantly the cost of each packaged semiconductor device and the resulting structure is more reliable than structures of the prior art.

US Patent:

57298947, Mar 24, 1998

Filed:

Jun 14, 1996

Appl. No.:

8/664146

Inventors:

Michael D. Rostoker - San Jose CA
Mark R. Schneider - San Jose CA
Edwin Fulcher - Palo Alto CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H05K 330
H05K 310
H01K 310

US Classification:

29832

Abstract:

A ball bump grid array package includes dies on one surface of a printed wiring board (PWB) and an array of ball bumps on the other surface of the PWB. The die is interconnected with the ball bumps by bond wires, traces on the one surface of the PWB, vias through the PWB and traces on the other surface of the PWB. Various die encapsulation schemes are discussed. The PWB is formed of FR4, BT, teflon or polyimide, or ceramic materials. The die may be connected to the traces on the one surface of the PWB with solder balls, rather than with bond wires. Two or more dies may be disposed on the one surface of the PWB, within the plastic molded body. The ball bumps on the other surface of the PWB may be arranged in a multiple grid pitch array--ball bumps within a central area being on a first pitch, and ball bumps without the central area being on a second pitch which is a multiple of the first pitch.

US Patent:

56104421, Mar 11, 1997

Filed:

Mar 27, 1995

Appl. No.:

8/412087

Inventors:

Mark R. Schneider - San Jose CA
Robert T. Trabucco - Los Altos CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2328
H01L 2310
H01L 2348

US Classification:

257787

Abstract:

A planar substrate is attached to a face of a semiconductor die. The semiconductor die is electrically connected to a printed wiring board and encapsulation material covers the peripheral edges of the planar substrate, semiconductor die, and means for interconnecting the die and printed wiring board. An exterior face of the planar substrate remains exposed and may be utilized in pick and place automatic assembly. The exterior face of the planar substrate may also be utilized for attachment of an external heat sink for improved heat transfer from the semiconductor device. The planar substrate may be comprised of silicon, ceramic, metal or any other stiff material so long as the temperature coefficient of expansion is similar to that of the semiconductor die. A flip-chip semiconductor die may also be utilized without a planar substrate wherein the nonactive face of the die is exposed.