Mark D Simpson

US Patent:

6346451, Feb 12, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/343912

Inventors:

Mark Simpson - Ossining NY
Theodore Letavic - Putnam Valley NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H01L 21331

US Classification:

438311, 438186, 257134, 257138, 257139, 257285, 257287, 257488

Abstract:

A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region. In order to provide improved breakdown voltage characteristics, a dielectric layer is provided over at least a part of the insulation region and the gate electrode, and a field plate electrode is provided over at least a part of the dielectric layer which is in direct contact with the insulation region, with the field plate electrode being connected to an electrode of the lateral transistor device.

US Patent:

6362504, Mar 26, 2002

Filed:

Nov 22, 1995

Appl. No.:

08/561960

Inventors:

Mark R. Simpson - White Plains NY

Assignee:

Philips Electronics North America Corporation - New York NY

International Classification:

H01L 29788

US Classification:

257317, 257316, 257321

Abstract:

A nonvolatile memory cell of the type having a single lateral transistor includes source and drain regions separated by a channel region. A floating gate is provided over at least the channel region and is separated therefrom by a gate oxide, with a control gate over the floating gate and insulated therefrom. By having the floating gate extend over substantially its entire length at a substantially constant distance from the surface of the device, and providing the floating gate and the surface with similarly-contoured corners adjacent ends of the source and drain regions alongside the channel region, the nonvolatile memory cell can be programmed and erased using lower voltages than those required by priorart devices.

US Patent:

6414365, Jul 2, 2002

Filed:

Oct 1, 2001

Appl. No.:

09/968121

Inventors:

Ted Letavic - Putnam Valley NY
Mark Simpson - White Plains NY

Assignee:

Koninklijke Philips Electronics N.V. - New York NY

International Classification:

H01L 2994

US Classification:

257409, 257347

Abstract:

A thin layer SOI high-voltage device in which the drift charge is depleted using a three-dimensional MOS capacitor structure. The drift region of the high-voltage semiconductor device is doped with a graded charge profile which increases from source-to-drain. The drift region is physically patterned to create a stripe geometry where individual SOI stripes. Each SOI stripe is individually circumscribed longitudinally by a dielectric layer wherein each dielectric layer is longitudinally circumscribed by field plates of a conducting multi-capacitor field plate layer which is electrically shorted to the substrate. The resultant structure is a thin drift-region stripe which is completely enclosed by a MOS field plate, resulting in three-dimensional depletion upon application of a bias voltage between the SOI stripe and its encapsulating field plates.

US Patent:

6642558, Nov 4, 2003

Filed:

Mar 20, 2000

Appl. No.:

09/531701

Inventors:

Ted Letavic - Putnam Valley NY
Mark Simpson - White Plains NY

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 27148

US Classification:

257219, 257285, 257657

Abstract:

Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

US Patent:

6847081, Jan 25, 2005

Filed:

Dec 10, 2001

Appl. No.:

10/015847

Inventors:

Theodore J. Letavic - Putnam Valley NY, US
Mark R. Simpson - White Plains NY, US

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 2701
H01L 2712
H01L 310392

US Classification:

257347, 257367, 257409, 257487, 257507

Abstract:

A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.

US Patent:

6927103, Aug 9, 2005

Filed:

Nov 12, 2003

Appl. No.:

10/706836

Inventors:

Ted Letavic - Putnam Valley NY, US
Mark Simpson - White Plains NY, US

Assignee:

Koninklijke Phillips Electronics N.V. - Eindhoven

International Classification:

H01L021/332

US Classification:

438140, 438529, 438551

Abstract:

Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies between different layers of a multiple layer device. In a preferred embodiment, the variations are such that the field strength is substantially constant along any horizontal or vertical cross section of the termination region.

US Patent:

7268046, Sep 11, 2007

Filed:

Dec 3, 2004

Appl. No.:

11/003991

Inventors:

Theodore J. Letavic - Putnam Valley NY, US
Mark R. Simpson - White Plains NY, US

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438287, 438257, 438262, 438275

Abstract:

A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.

US Patent:

20030107050, Jun 12, 2003

Filed:

Dec 10, 2001

Appl. No.:

10/015640

Inventors:

Theodore Letavic - Putnam Valley NY, US
Mark Simpson - White Plains NY, US
Lucian Albu - New York NY, US
Satyendranath Mukherjee - Yorktown Heights NY, US

Assignee:

Koninklijke Philips Electronics N.V.

International Classification:

H01L029/74

US Classification:

257/148000

Abstract:

A high frequency high voltage semiconductor device having a shifted doping profile and method for forming the same are provided. Specifically, the present invention provides a semiconductor device (