Mark Tran

US Patent:

6355381, Mar 12, 2002

Filed:

Sep 25, 1998

Appl. No.:

09/160740

Inventors:

Mark Thiec-Hien Tran - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5, 430322, 430323

Abstract:

A process for fabricating a photolithograpic mask by etching a silicon layer and then forming an absorbent silicide. A protective oxide layer is sputtered on a substrate and is then covered by a layer of silicon. Silicon members and reflective regions are formed from the layer of silicon. Defects in the silicon members are repaired. A layer of nickel is deposited over the silicon members and the reflective regions. The silicon members are converted into an absorbent silicide at a low temperature. The remaining metal and the protective oxide layers are removed resulting in a photolithographic mask.

US Patent:

6630273, Oct 7, 2003

Filed:

Oct 4, 2001

Appl. No.:

09/971862

Inventors:

Mark Thiec-Hien Tran - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G03F 900

US Classification:

430 5

Abstract:

A process for fabricating a photolithograpic mask by etching a silicon layer and then forming an absorbent silicide. A protective oxide layer is sputtered on a substrate and is then covered by a layer of silicon. Silicon members and reflective regions are formed from the layer of silicon. Defects in the silicon members are repaired. A layer of nickel is deposited over the silicon members and the reflective regions. The silicon members are converted into an absorbent silicide at a low temperature. The remaining metal and the protective oxide layers are removed resulting in a photolithograpic mask.

US Patent:

62777653, Aug 21, 2001

Filed:

Aug 17, 1999

Appl. No.:

9/376510

Inventors:

Peng Cheng - Campbell CA
Brian S. Doyle - Cupertino CA
Chien Chiang - Fremont CA
Mark Thiec-Hien Tran - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2131

US Classification:

438773

Abstract:

A low dielectric constant material, suitable for use as an interlayer dielectric in microelectronic structures includes a porous silicon oxide layer. In a further aspect of the present invention, a porous oxide of silicon is formed by the room temperature oxidation of porous silicon. The room temperature oxidation is achieved by exposing a porous silicon layer to a solution of hydrochloric acid, hydrogen peroxide, and water, in the presence of a metal catalyst.