Mark C Walker

US Patent:

6863788, Mar 8, 2005

Filed:

Jul 29, 2002

Appl. No.:

10/206472

Inventors:

Guy L. Fredrickson - Golden CO, US
Eric Groat - Williamsville NY, US
Thomas Mroz - Kenmore NY, US
Alan Ulicny - Amherst NY, US
Mark F. Walker - Richmond VA, US

Assignee:

Alcoa Inc. - Pittsburgh PA

International Classification:

C25C007/02

US Classification:

2042431, 204279

Abstract:

An electrolytic cell for the reduction of aluminum having a layer of interlocking cathode tiles positioned on a cathode block. Each tile includes a main body and a vertical restraining member to prevent movement of the tiles away from the cathode block during operation of the cell. The anode of the electrolytic cell may be positioned about 1 inch from the interlocking cathode tiles.

US Patent:

52747999, Dec 28, 1993

Filed:

Jan 4, 1991

Appl. No.:

7/638167

Inventors:

William A. Brant - Boulder CO
David C. Stallmo - Boulder CO
Mark Walker - Los Gatos CA
Albert Lui - San Jose CA

Assignee:

Array Technology Corporation - Boulder CO

International Classification:

G06F 1110

US Classification:

395575

Abstract:

A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, during idle time for relevant storage units of the storage system, an error-correction block is computed for each "pending" data block on the copyback cache storage unit, and the data block and corresponding error-correction block are copied to their proper location in the RAID system. The copyback cache storage unit in effect stores "peak load" Write data and then completes the actual Write operations to the RAID system during relatively quiescent periods of I/O accesses by the CPU. In a second embodiment of the invention, after Write data is logged to the copyback cache storage unit, normal Read-Modify-Write operation by the RAID system controller continues in overlapped fashion with other CPU I/O accesses using Write data in the controller's buffer memory.

US Patent:

20200092254, Mar 19, 2020

Filed:

Oct 25, 2019

Appl. No.:

16/664657

Inventors:

- LOUISVILLE CO, US
Michael Glenn - Golden CO, US
Brian A. Scriber - Lafayette CO, US
Brady Johnson - Madrid, ES
Mark Deazley - Westminster CO, US
Darshak Thakore - Broomfield CO, US
Mark Walker - Superior CO, US

International Classification:

H04L 29/06
G06N 3/04
H04L 12/66
H04L 12/931

Abstract:

A wireless communication system includes an external provider subsystem and an electronic network subsystem in operable communication with the external provider subsystem. The electronic network subsystem is configured to provide a first microservice and a second microservice different from the first microservice. The wireless communication system further includes an in-home subsystem (i) separate from the external provider subsystem, (ii) in operable communication with the electronic network subsystem, and (iii) including a first micronet and a second micronet different from the first micronet. The first micronet is configured to operably interact with the first microservice, and the second micronet is configured to operably interact with the second microservice. The wireless communication system further includes at least one electronic device configured to operably connect with one of the first micronet and the second micronet.