Mark Russell Whitaker

US Patent:

7526693, Apr 28, 2009

Filed:

Mar 9, 2006

Appl. No.:

11/371661

Inventors:

David J. Willis - Murray UT, US
Matthew Austin Tyler - Kaysville UT, US
Justin Mark Gedge - Eagle Mountain UT, US
Mark R. Whitaker - Draper UT, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

G01R 31/28

US Classification:

714724, 714 36, 714 48, 714740, 714742, 702 98, 702 85, 3652257, 36518503, 712 39, 712 40, 712 43, 31856817, 318590, 31840009, 31840011, 710 14

Abstract:

A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode. Depending on whether or not signal(s) satisfying predetermined criteria are applied to at least one of the control I/O pins, the controller will cause the circuit to enter one of two or more post-initial operation modes. Accordingly, by initializing the controller, and by controlling a signal on the control I/O pin(s), the operating mode of the circuit may be controlled. In one embodiment, a given control pin might be configurable to be both analog and digital, depending on the circuit's operation mode.

US Patent:

20120007720, Jan 12, 2012

Filed:

Jul 9, 2010

Appl. No.:

12/833817

Inventors:

Mark R. Whitaker - Colorado Springs CO, US

Assignee:

RAMTRON INTERNATIONAL CORPORATION - Colorado Springs CO

International Classification:

H04Q 5/22
G11C 19/00

US Classification:

340 1051, 377 78

Abstract:

A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.

US Patent:

20120007721, Jan 12, 2012

Filed:

Jul 9, 2010

Appl. No.:

12/833836

Inventors:

Mark R. Whitaker - Colorado Springs CO, US
Doug D. Moran - Carlsbad CA, US
Robert John Clarke - Heathpool, AU
Alexander Antony John Roach - Kent Town, AU

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

H04Q 5/22

US Classification:

340 1051

Abstract:

A fast block write command includes providing an RFID tag having a memory, and using a stored address pointer to point to a known address in the memory, wherein the stored address pointer points to a starting address at a known safe block in the memory. The method is performed without an intermediate buffer. The received data is written to the known safe block and a cyclic redundancy check is computed on the received data. If the cyclic redundancy check matches, the received data is retained and the stored address pointer is updated. If the cyclic redundancy check does not match, the stored address pointer is kept for a future write operation. Further block writes can be disallowed after an initial successful block write.

US Patent:

20120007722, Jan 12, 2012

Filed:

Jul 9, 2010

Appl. No.:

12/833845

Inventors:

Mark R. Whitaker - Colorado Springs CO, US
Danny Lee Secrest - Colorado Springs CO, US

Assignee:

RAMTRON INTERNATIONAL CORPORATION - Colorado Springs CO

International Classification:

H04Q 5/22

US Classification:

340 1051

Abstract:

A method of operating a memory in an RFID application includes locating a memory pointer at a fixed read/writeable memory location in the memory, determining a range of a pedigree buffer, initializing the memory pointer to a lowest value in the range, providing a second memory location that serves as a trigger address for an indirect write, and writing to a next location in the pedigree buffer by directing write data to the trigger address, which is then automatically written at a location pointed to by the memory pointer.

US Patent:

20120007723, Jan 12, 2012

Filed:

Jul 9, 2010

Appl. No.:

12/833861

Inventors:

Mark R. Whitaker - Colorado Springs CO, US
Leslie Joseph Marentette - Newmarket, CA

Assignee:

Ramtron International Corporation - Colorado Springs CO

International Classification:

H04Q 5/22

US Classification:

340 1051

Abstract:

A memory circuit includes a memory, a memory access control circuit coupled to the memory, an RFID interface coupled to the memory access control circuit, a secondary interface coupled to the memory access control circuit, and an interrupt manager coupled to the memory access control circuit, the RFID interface, and the secondary interface.

US Patent:

59364114, Aug 10, 1999

Filed:

Nov 28, 1997

Appl. No.:

8/980325

Inventors:

Stephen C. Jacobsen - Salt Lake City UT
Michael G. Mladejovsky - Salt Lake City UT
Mark R. Whitaker - Salt Lake City UT
Brian J. Maclean - Salt Lake City UT

Assignee:

Sarcos L.C. - Salt Lake City UT

International Classification:

G01R 2726

US Classification:

324662

Abstract:

A method and apparatus for measuring displacement of one location of a structure, relative to another, spaced apart location. The apparatus includes a first array of conductive elements disposed on the structure and attached at said one location; a second array of conductive elements disposed on the structure adjacent the first array and attached at said other, spaced-apart location such that displacement of said one location with respect to said other, spaced-apart location can be measured by measuring the first array position with respect to the second array position; a source for supplying an electric current to the first and the second array of conductive elements to develop a unique charge between each conductive element of the first array and each respective conductive element of the second array, wherein the unique charge that is stored between each pair of conductive elements changes when the relative position of the first array changes with respect to the second array and the change in charges corresponds to the displacement of the one location with respect to the other, spaced apart location.

US Patent:

56278608, May 6, 1997

Filed:

Jun 1, 1995

Appl. No.:

8/456510

Inventors:

Carol A. McKinny - Delray Beach FL
Christopher B. Rausch - Boynton Beach FL
Mark L. Oliboni - Boynton Beach FL
Mark R. Whitaker - Pflugerville TX
Mark H. Babcock - Austin TX
Tuan S. Hoang - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 2506

US Classification:

375317

Abstract:

A peak and valley detection system and method are shown for a selective call receiving device (10). The peak and valley detection system quickly and accurately detects and tracks to the peak and valley of a two level and/or four-level signal. A signal value representing a received signal is compared by a CPU (28) to the sum of a peak variable and attack constant. The peak variable is updated to a first value if the received signal value is less than the sum and is updated to a second value if the received signal value is not less than the sum. Similarly, the received signal is compared by the CPU (28) to a difference between a valley variable and attack constant. The valley variable is updated to a third value if the received signal value is greater than the difference value and updated to a fourth value if the received signal value is not greater than the difference value. The peak and valley variables attack and decay at non-constant rates and independently of one another.