Mark J Winter

US Patent:

7852787, Dec 14, 2010

Filed:

Mar 24, 2008

Appl. No.:

12/054237

Inventors:

Peter Gelbman - Kirkland WA, US
Mark Adrian Winter - Seattle WA, US

Assignee:

Clearwire Legacy LLC - Kirkland WA

International Classification:

H04L 12/28

US Classification:

370254, 370401

Abstract:

A network having an access service network (“ASN”) configured to provide full mobility to mobile stations located within a service area. The ASN includes a Layer 2 or data link layer network that is larger, incorporates more nodes, or carries more data communications than Layer 2 networks incorporated in prior art ASNs. Data communications to and from the mobile stations are routed inside the ASN across the Layer 2 network which transports the data communication using a Layer 2 protocol. If the network includes another ASN located adjacent to the first ASN, the two ASNs may communicate directly with one another over a Layer 2 connection. If the network includes another ASN that is not adjacent to the first, Mobile Internet Protocol components may be included in the ASNs and configured to provide mobility between ASNs.

US Patent:

8126428, Feb 28, 2012

Filed:

Aug 5, 2008

Appl. No.:

12/186451

Inventors:

Peter Gelbman - Kirkland WA, US
Jeffrey Sewell - Kirkland WA, US
Mark Winter - Seattle WA, US

Assignee:

Clearwire Corporation - Kirkland WA

International Classification:

H04M 11/00
H04M 3/42

US Classification:

455406, 4554141

Abstract:

A subscriber management system for a communication system having a radio access network coupled to by a gateway node to a packet switched network. The system consolidates three prior art subscriber management system components, a DPI device, a QoS Policy Manager , and an Application Manager , into a DPI platform. The system also relocates functions to the DPI platform that were previously provided by the gateway node in prior art networks. Specifically, an Accounting Client , a Hotlining function , and a QoS SFA function are located to the DPI platform. By consolidating network components and relocating functions to the DPI platform, the number of control interfaces in the network can be reduced. Further, network components produced by different vendors may be integrated more easily. A method of implementing hotlining in the system is also provided.

US Patent:

8451640, May 28, 2013

Filed:

Jan 10, 2011

Appl. No.:

12/930581

Inventors:

Christopher Gronlund - Kent WA, US
Mark Winter - Seattle WA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 15/00

US Classification:

365 4917, 365 491, 365 4916

Abstract:

A content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

US Patent:

20120146672, Jun 14, 2012

Filed:

Jan 6, 2011

Appl. No.:

12/930470

Inventors:

Mark Winter - Seattle WA, US
Eric Hall - Bellevue WA, US

Assignee:

BROADCOM CORPORATION - IRVINE CA

International Classification:

G01R 31/26
G01R 31/3187

US Classification:

3247503

Abstract:

Disclosed is a monitoring system that includes at least one performance monitor integrated into a semiconductor die. The performance monitor comprises at least one ring oscillator that includes a plurality of stages. Each stage comprises at least one memory device. In one embodiment, the performance monitor may also include a setting circuit that has a burn-in input and an enable input. The setting circuit is capable of setting an input signal of the at least one ring oscillator to a reference voltage level. The performance monitor is configured to produce a ring delay that is characterized by a performance of the at least one memory device. The ring delay may be utilized to scale an operating voltage of the at least one memory device on the semiconductor die.

US Patent:

20130250642, Sep 26, 2013

Filed:

May 24, 2013

Appl. No.:

13/901970

Inventors:

Mark Winter - Seattle WA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G11C 15/04

US Classification:

365 4917

Abstract:

According to one disclosed embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes a plurality of bit cells implementing a stacked architecture. Each bit cell comprises a pair of stacked storage elements in a first column and a compare circuit, coupled to the pair of stacked storage elements and a matchline of the CAM system, situated in a second column. The stacked architecture results in a reduced matchline length, thereby reducing CAM system power consumption and increasing CAM system speed. In a further embodiment, a content addressable memory (CAM) system configured for reduced power consumption and increased speed includes storing encoded data in a pair of stacked storage elements.

US Patent:

20180218769, Aug 2, 2018

Filed:

Mar 29, 2018

Appl. No.:

15/940800

Inventors:

- Singapore, SG
Mark J. Winter - Seattle WA, US

Assignee:

Avago Technologies General IP (Singapore) Pte. Ltd . - Singapore

International Classification:

G11C 11/419
G11C 11/412
G11C 5/14

Abstract:

A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

US Patent:

20170294223, Oct 12, 2017

Filed:

Apr 21, 2016

Appl. No.:

15/135133

Inventors:

- Irvine CA, US
Mark J. Winter - Seattle WA, US

Assignee:

BROADCOM CORPORATION - Irvine CA

International Classification:

G11C 11/419

Abstract:

A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.

US Patent:

20160093399, Mar 31, 2016

Filed:

Nov 6, 2014

Appl. No.:

14/534548

Inventors:

- Irvine CA, US
Yifei ZHANG - Edina MN, US
Carl MONZEL - Eagan MN, US
Mark Jon WINTER - Seattle WA, US

International Classification:

G11C 29/04
G11C 7/12

Abstract:

A device for monitoring process variations across memory bitcells includes a bitcell inverter that provides an output voltage to be used for identifying skewed corners of the memory bitcells. A first comparator compares the output voltage with a first reference voltage, and a second comparator compares the output voltage with a second reference voltage. The first and the second comparators generate a corner code based on comparison results.