Markus Loose

US Patent:

7046284, May 16, 2006

Filed:

Feb 11, 2004

Appl. No.:

10/776952

Inventors:

Lester J. Kozlowski - Simi Valley CA, US
Markus Loose - Thousand Oaks CA, US

Assignee:

Innovative Technology Licensing LLC - Thousand Oaks CA

International Classification:

H04N 5/335

US Classification:

348308, 348241

Abstract:

A CMOS imager system including an active pixel sensor having an access supply which provides distributed feedback, a column buffer (having gain and FPN suppression), and an A/D converter co-located with the sensor such that the effective transmission path between the column buffer (or optional analog PGA) and the A/D converter acts as a resistor, rather than a reactance. The system may further include both an analog gain amplifier stage and a digital programmable amplifier stage.

US Patent:

7417675, Aug 26, 2008

Filed:

May 12, 2003

Appl. No.:

10/436945

Inventors:

Markus Loose - Thousand Oaks CA, US

Assignee:

Altasens, Inc. - Westlake Village CA

International Classification:

H04N 9/64

US Classification:

348243, 348308, 348374

Abstract:

An image sensing system includes an image sensor and a black clamping circuit which reside on the same substrate. Particular embodiments use common components for both imaging and black clamping, and digital control of an analog black clamp function.

US Patent:

7443435, Oct 28, 2008

Filed:

Jul 7, 2004

Appl. No.:

10/886319

Inventors:

Markus Loose - Thousand Oaks CA, US

Assignee:

AltaSens, Inc. - Westlake Village CA

International Classification:

H04N 3/14
H04N 5/335
H03G 3/00
H03G 3/10

US Classification:

348294, 348300, 348301, 3482291, 348302, 348308, 330278, 330279

Abstract:

A column amplifier architecture having automatic gain selection for CMOS image sensors, which reduces the effect of analog noise, while maintaining a system's dynamic range. A comparator compares an amplified column buffer output signal to a reference voltage. The output of the comparator controls the gain of the amplifier based on the result of the comparison. Initially, a high column buffer gain is selected. For small signals, the output of the column buffer stays below the reference voltage and the output signal stays within the system's dynamic range. For larger signals, the column buffer output will exceed the reference voltage (and also the system's dynamic range) and therefore the comparator output switches states, which selects the low-gain setting. Multiple gain levels may be implemented, if desired.

US Patent:

7525586, Apr 28, 2009

Filed:

May 12, 2003

Appl. No.:

10/436947

Inventors:

Markus Loose - Thousand Oaks CA, US

Assignee:

Altasens, Inc. - Westlake Village CA

International Classification:

H04N 3/14
H04N 5/335

US Classification:

348308, 348302

Abstract:

Multiple scanning modes are provided for an array of electromagnetic radiation sensors. In the preferred implementation both selectable subarrays and the overall array can be read out and reset in any desired order, including interrupting a full array scan for a subarray scan and then resuming the full array scan.

US Patent:

20040227832, Nov 18, 2004

Filed:

May 12, 2003

Appl. No.:

10/436946

Inventors:

Markus Loose - Thousand Oaks CA, US

Assignee:

INNOVATIVE TECHNOLOGY LICENSING, LLC.

International Classification:

H04N005/335

US Classification:

348/308000

Abstract:

Individual pixel reset circuits for an array of electromagnetic radiation sensors include a reset transistor connected to enable a reset of the pixel's sensor, and a logic gate connected to activate the reset transistor in response to a plurality of array reset signals. The logic gate can be implemented with only three transistors, and enables the selection of individual pixels for reset.

US Patent:

20040252209, Dec 16, 2004

Filed:

Jun 11, 2003

Appl. No.:

10/460014

Inventors:

Markus Loose - Thousand Oaks CA, US

Assignee:

Innovative Technology Licensing,LLC

International Classification:

H04N005/335

US Classification:

348/255000

Abstract:

A digital programmable gain stage for adjusting the gain of an input signal. A fine gain adjustment circuit sets gains between 1 and 2 (0-6 dB). A coarse gain adjustment stage adjusts the gain by multiples of 2. An input signal is multiplied by the fine gain adjustment factor, and then the coarse gain adjustment stage multiplies or divides the result by a multiple of 2. This architecture allows for gain adjustments from -24 dB to +66 dB in steps of 0.006 dB, using 14 bit resolution. Any number of gain ranges and gain resolutions are feasible with the current design by changing the bit width of the individual components.

US Patent:

20090185044, Jul 23, 2009

Filed:

Mar 30, 2009

Appl. No.:

12/414592

Inventors:

Markus LOOSE - Thousand Oaks CA, US

Assignee:

Altasens, Inc. - West Lake Village CA

International Classification:

H04N 5/225
H04N 5/228

US Classification:

3482181, 3482221, 348E05024, 348E05031

Abstract:

Multiple scanning modes are provided for an array of electromagnetic radiation sensors. In the preferred implementation both selectable subarrays and the overall array can be read out and reset in any desired order, including interrupting a full array scan for a subarray scan and then resuming the full array scan.

US Patent:

20090278951, Nov 12, 2009

Filed:

May 8, 2008

Appl. No.:

12/151917

Inventors:

Markus Loose - Thousand Oaks CA, US
Ying Huang - Newbury Park CA, US
Giuseppe Rossi - Los Angeles CA, US
Roberto Marchesini - Santa Monica CA, US
Gaurang Patel - Newbury Park CA, US
Qianjiang (Bob) Mao - Chino Hills CA, US
Gregory Chow - Camarillo CA, US
John Wallner - Calabasas CA, US

International Classification:

H04N 5/228
H04N 5/225
H04N 5/04
H03L 7/00

US Classification:

3482221, 348262, 348500, 348540, 348E05031, 348E05024

Abstract:

Apparatus and methods for synchronizing a plurality of image sensors in a video camera system. In one embodiment, a method includes generating a video sync signal, and resetting at least one internal clock divider in each image sensor in synchronization with the video sync signal at the beginning of each video frame. Another embodiment of a method of synchronizing a plurality of image sensors in a video camera system includes detecting a phase state of a signal of at least one internal clock divider in each sensor, wherein the phase state is relative to a system sync signal, and selecting a video output signal for each sensor based on the detected phase state of the at least one internal divider. In a third embodiment, the method includes asserting an asynchronous reset signal, stopping the system clocks in the system, de-asserting the asynchronous reset signal, while the system clocks are stopped, and restarting the system clocks. Each method may be used individually, or the methods can be combined in any combination. A video camera apparatus is also described.