Jack T. Wong - Fremont CA Fabiano Fontana - Santa Clara CA Martha Chan - Cupertino CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 1901 H03K 190175
US Classification:
326 17
Abstract:
A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.
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